PLL与MMCM区别

落日映苍穹つ 2023-02-16 15:23 12阅读 0赞

[设计方法指南][Link 1]

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**PLL输出时钟和输入时钟之间的相位关系是未知的，但MMCM是可以选择对齐输入输出相位的。**

**同时PLL只有两个输出时钟，而MMCM有6个。**

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在Xilinx的FPGA中，时钟管理器称为Clock Management，简称CMT。我们所用到的DCM / PLL / MMCM都包含在CMT中。

DCM是比较早的FPGA中使用的，某些Sparten-3和Virtex-4，后面的器件不再使用了。在Virtex-4中，CMT包括一个PLL和两个DCM。DCM的核心是DLL，即延迟Locked Loop，它是一个数字模块，可以产生不同相位的时钟，分频，倍频，相位动态调整等，但精度有限。

PLL就是锁相环，这个大家应该都熟悉，时钟倍频，分频，调节相位等都是可以用PLL，而且PLL是一个模拟电路，它产生的频率比DCM更加准备，jitter也更好，但PLL无法动态调整相位。

MMCM是混合模式时钟管理器，它的官方解释是：这是一个PLL，上面加上了DCM的一小部分以进行精细的相移（这就是它的混合模式的原因-PLL是模拟的，但是相移是数字的） 。它是在PLL的基础上加上了相位动态调整功能，因为PLL是模块电路，而动态调相是数字电路，所以叫混合模式。MMCM是在Virtex-6中被约会的，而且Virtex-6中也只有MMCM。

7s FPGA中，最高包含了24个CMT，每个CMT包含一个MMCM和一个PLL。Ultrascale中，一个CMT包含一个MMCM和两个PLL。

MMCM相对PLL的优势就是相位可动态调整，但PLL占用的面积更小。

[http://xilinx.eetrend.com/blog/2019/100046618.html][http_xilinx.eetrend.com_blog_2019_100046618.html]

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参考输入频率：

MMCM最低10MHz,PLL最低要求70MHz!

参考：

Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinouts  Product Specification User Guide

[Link 1]: https://china.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/c_ug949-vivado-design-methodology.pdf
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[20200610145108209.png]: https://img-blog.csdnimg.cn/20200610145108209.png
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[http_xilinx.eetrend.com_blog_2019_100046618.html]: http://xilinx.eetrend.com/blog/2019/100046618.html
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