Verilog D锁存器

男娘i 2024-04-18 13:58 47阅读 0赞

**简介：**  
用门级描述的方法写一个D锁存器，并对其逻辑功能进行测试。D锁存器的真值表，逻辑表达式和逻辑电路图如下：  
![在这里插入图片描述][20200724114003179.png]

**Verilog代码实现：**

/*---------------------------------------------- Filename: D_latch.v Function: 逻辑门控D锁存器(方案1的描述，方案2与之类似) Author: Zhang Kaizhou Date: 2020-7-22 09:40:45 ----------------------------------------------*/
    module D_latch(q, nq, en, d);
    	output q, nq;
    	input en, d;
    	wire wnr, wns, wq, wnq, nd; //内部连线
    	
    	//门级描述
    	nor nd1(wq, wns, wnq), nd2(wnq, wnr, wq);
    	and ad1(wns, nd, en), ad2(wnr, en, d);
    	nor nr1(nd, d);
    	assign q = wq;
    	assign nq = wnq;
    endmodule

/*------------------------------------- Filename: D_latch_tb.v Function: 测试逻辑门控D锁存器 Author: Zhang Kaizhou Date: 2020-7-22 09:40:37 -------------------------------------*/
    `timescale 1ns/1ns
    module D_latch_tb(q, nq);
    	output q, nq;
    	reg en, d;
    	
    	initial
    	begin
    		#100 en = 1'b1; d = 1'b0;
    		#100 d = 1'b1;
    		#100 d = 1'b0;
    		#200 en = 1'b0;
    		#100 d = 1'b1;
    		#100 en = 1'b1;
    		#500 $stop;
    	end
    	
    	D_latch m0(.q(q), .nq(nq), .en(en), .d(d));
    endmodule

**仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]

**总结：**  
由上面的仿真结果可知，D锁存器的基本逻辑功能(数据保持以及输出随D变化而变)已实现。

[20200724114003179.png]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/18/92eff88ddd104acdb68e2c0ff8e06d2f.png
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/18/a323ddd02a0e409dae1e8ba127983d80.png