Veriolg R'S'锁存器

喜欢ヅ旅行 2024-04-18 13:44 57阅读 0赞

**简介：**  
写一个R’S’锁存器，其基本功能为：置0 置1 保持。R’S’锁存器的真值表，逻辑表达式，逻辑电路图如下：  
![在这里插入图片描述][20190907153945727.png]  
**Verilog代码实现：**

/*-------------------------------------
    Filename: RS_latch.v
    Function: 用两个与非门构成的R'S'锁存器
    Author: Zhang Kaizhou
    Date: 2019-9-7 12:43:05
    -------------------------------------*/
    module RS_latch(q, nq, nr, ns);
    	output q, nq;
    	input nr, ns;
    	wire wq, wnq;
    	
    	//门级描述
    	nand nd1(wq, ns, wnq), nd2(wnq, nr, wq);
    	assign q = wq;
    	assign nq = wnq;
    endmodule

/*-------------------------------------
    Filename: RS_latch_tb.v
    Function: 测试RS_latch逻辑功能
    Author: Zhang Kaizhou
    Date: 2019-9-7 15:44:51
    -------------------------------------*/
    `timescale 1ns/1ns
    module RS_latch_tb(q, nq);
    	output q, nq;
    	reg nr, ns;
    	
    	initial
    	begin
    		#100 nr = 1'b0; ns = 1'b0;
    		#100 nr = 1'b0; ns = 1'b1;
    		#100 nr = 1'b1; ns = 1'b0;
    		#100 nr = 1'b1; ns = 1'b1;
    		#1000 $stop;
    	end
    	
    	RS_latch m0(.q(q), .nq(nq), .nr(nr), .ns(ns));
    endmodule

**仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]  
**总结：**  
由以上结果易知R’S’锁存器的三个基本功能均已实现。但是由真值表以及仿真波形图可知，该结构的锁存器存在一个缺陷，即当R’和S’同时为0时锁存器处于非稳态QQ’ = 11(锁存器的两个稳态为QQ’ = 01和QQ’ = 10)。该缺陷可通过D锁存器的结构来解决。

[20190907153945727.png]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/18/04ca8fd2ef264e77867fb3f1b9cd25de.png
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]: https://image.dandelioncloud.cn/pgy_files/images/2024/04/18/bf2cd10f34a1495d8f3ca61a2b02aa38.png