Verilog实现一个8位带进位全加器

刺骨的言语ヽ痛彻心扉 2023-08-17 17:33 111阅读 0赞

**项目简介：**  
用Verilog语言实现一个8位带进位全加器。顶层采用结构描述的方法用8个1位全加器来实现一个8位带进位全加器，底层的1位全加器采用行为描述的方法来实现。  
**代码实现：**

/*--------------------------------------------------------------
    Filename: adder_8.v
    Function: 实现两个8位二进制数的带进位加法运算(输出和S最大为256)
    Author: Zhang Kaizhou
    Date: 2019-10-1 19:42:22
    --------------------------------------------------------------*/
    //8位加法器顶层模块
    module adder_8(s, cout, a, b, cin);
    	//输入输出端口及变量定义
    	output [7 : 0] s;
    	output cout;
    	input [7 : 0] a, b;
    	input cin;
    	wire [6 : 0] carry;
    	
    	//采用结构描述的方式实现一个8位加法器
    	fulladder m0(s[0], carry[0], a[0], b[0], cin);
    	fulladder m1(s[1], carry[1], a[1], b[1], carry[0]);
    	fulladder m2(s[2], carry[2], a[2], b[2], carry[1]);
    	fulladder m3(s[3], carry[3], a[3], b[3], carry[2]);
    	fulladder m4(s[4], carry[4], a[4], b[4], carry[3]);
    	fulladder m5(s[5], carry[5], a[5], b[5], carry[4]);
    	fulladder m6(s[6], carry[6], a[6], b[6], carry[5]);
    	fulladder m7(s[7], cout, a[7], b[7], carry[6]);
    endmodule
    
    //1位全加器模块
    module fulladder(s, cout, a, b, cin);
    	//输入输出端口定义
    	output s, cout;
    	input a, b, cin;
    	
    	//采用行为描述的方式实现1位全加器
    	assign s = a ^ b ^ cin;
    	assign cout = a & b | a & cin | b & cin;
    endmodule

/*---------------------------------
    Filename: adder_8_t.v
    Function: 测试adder_8模块逻辑功能
    Author: Zhang Kaizhou
    Date: 2019-10-1 19:58:22
    ---------------------------------*/
    `timescale 1ns/1ns
    module adder_8_t(s, cout);
    	//端口及变量定义
    	output [7 : 0] s;
    	output cout;
    	reg [7 : 0] a, b;
    	reg cin;
    	
    	initial
    	begin
    		#100 a = 8'b0000_0000; b = 8'b0000_0000; cin = 1'b0; //0 + 0 + 0= 0
    		#100 a = 8'b0000_0001; b = 8'b0000_0001; cin = 1'b1; //1 + 1 + 1 = 3
    		#100 a = 8'b0010_0000; b = 8'b0010_0011; cin = 1'b1; //32 + 35 + 1 = 68
    		#100 a = 8'b1111_1100; b = 8'b0000_0011; cin = 1'b0; //252 + 3 + 0 = 255
    		#100 a = 8'b1111_1100; b = 8'b0000_0011; cin = 1'b1; //252 + 3 + 1 = 256
    		#100 a = 8'b1111_1100; b = 8'b0000_1000; cin = 1'b0; //252 + 8 + 0 = 260 (溢出错误)
    		#500 $stop;
    	end
    	
    	adder_8 m0(.s(s), .cout(cout), .a(a), .b(b), .cin(cin));
    endmodule

**Modelsim仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]  
**总结：**  
由上面的仿真波形易知，以上代码实现了一个8位全加器的逻辑功能，达到了设计预期。

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