Verilog多输出FSM的实现

叁歲伎倆 2023-06-06 08:13 19阅读 0赞

**简介：**  
本篇主要介绍具有多个输出的有限状态机的Verilog实现方式。仍以上一篇[《Verilog可综合FSM的实现》][Verilog_FSM]中所描述的4状态FSM为例进行介绍。  
**代码实现：**

/*----------------------------------------
    Filename: fsm.v
    Function: 具有多个输出的FSM的实现(可综合)
    Author: Zhang Kaizhou
    Date: 2019-10-10 17:03:23
    -----------------------------------------*/
    module fsm(y3, y2, y1, state, clk, reset, a);
    	//定义输入输出端口
    	output y3, y2, y1;
    	output [3 : 0] state;
    	input clk, reset, a;
    	
    	//定义状态寄存器
    	reg y3, y2, y1;
    	reg [3 : 0] state, nextstate;
    	
    	//状态编码
    	//parameter idle = 2'b00, start = 2'b01, stop = 2'b10, clear = 2'b11; //格雷码
    	parameter idle = 4'b1000, start = 4'b0100, stop = 4'b0010, clear = 4'b0001; //独热码(推荐)
    	
    	//状态转移
    	always@(posedge clk)
    	begin
    		if(!reset) state <= idle;
    		else state <= nextstate;
    	end
    	
    	//产生下一个状态nextstate的组合逻辑
    	always@(state or a)
    	begin
    		case(state)
    			idle: if(a) nextstate = start; else nextstate = idle;
    			start: if(!a) nextstate = stop; else nextstate = start;	   
    			stop: if(a) nextstate = clear; else nextstate = stop;	  
    			clear: if(!a) nextstate = idle; else nextstate = clear;
    			default: nextstate = 2'bxx;
    		endcase
    	end
    	
    	//产生输出的组合逻辑
    	always@(state)
    	begin
    		if(state == start || state == stop) y3 = 1;
    		else y3 = 0;
    		if(state == start || state == clear) y2 = 1;
    		else y2 = 0;
    		if(state == start || state == stop) y1 = 1;
    		else y1 = 0;
    	end
    endmodule

/*---------------------------
    Filename: fsm_t.v
    Function: 有限状态机测试程序
    Author: Zhang Kaizhou
    Date: 2019-10-10 17:03:33
    ---------------------------*/
    `timescale 1ns/1ns
    `define PERIOD 5
    module fsm_t(y3, y2, y1, state);
    	output y3, y2, y1;
    	output [3 : 0] state;
    	reg clk, reset, a;
    	
    	fsm m0(.y3(y3), .y2(y2), .y1(y1), .state(state), .clk(clk), .reset(reset), .a(a));
    	
    	always
    	begin
    		clk = 0;
    		#`PERIOD clk = ~clk;
    	end
    	
    	initial
    	begin
    		#100 reset = 0; a = 0;
    		#100 reset = 1; a = 1;
    		#100 a = 0;
    		#100 a = 1;
    		#100 a = 0;
    		#500 $stop;
    	end
    endmodule

**ModelSim仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]  
**总结：**  
对比上一篇《Verilog可综合FSM的实现》中的代码实现，本篇中的主要区别为将下一状态的产生以及输出结果的产生分别采用不同的组合逻辑来实现。这样做对于具有多个输出的FSM能够更加高效地进行代码的测试验证。由上面的仿真波形可知，该FSM的基本逻辑功能已实现。

[Verilog_FSM]: https://blog.csdn.net/weixin_38679924/article/details/102460729
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]: /images/20230601/1f3ce71caeef47a5857fb9f3daaa3079.png