7 Series FPGAs Configuration

末蓝、 2023-01-17 07:46 123阅读 0赞

主动加载或被动

串行（精简IO）

并行（速度快/性能高）

可以被无限配置/每次上电都会进行配置操作（掉电不存储）

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有三个配置模式选择引脚：**M0/M1/M2**

![20210427193320526.png][]

主和从是相对于配置时钟CCLK的方向来说的，谁驱动CCLK谁就是主

CCLK三态弱上拉

JTAG接口一致有效和配置引脚状态无关

![20210427193845164.png][]

**DIN引脚为复用**，用于选择Matser SPI位宽

![2021042719423359.png][]

Matser SPI 支持下降沿捕获数据，优化时钟，因此可以支持更高的速率

**配置BANK电压选择引脚：CFGBVS**

当CFGBVS为LOW(GND)时，选择配置电压1.8V/1.5V，对应的配置bank(0(JTAG)/14/15)需要设置电压在1.8V/1/5V  
当CFGBVS为VCCO\_0时，选择配置电压3.3V/2.5V

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[20210427193320526.png]: /images/20221021/8062fa4f43c641f098420333c985f042.png
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[2021042809393716.png]: /images/20221021/dad8529c78174c6ba2636c80f15aa0f1.png
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