一起学习用Verilog在FPGA上实现CNN----(六)SoftMax层设计

r囧r小猫 2023-09-24 17:21 44阅读 0赞

# 1 SoftMax层设计 #

## 1.1 softmax ##

SoftMax函数的作用是输入归一化，计算各种类的概率，即计算0-9数字的概率，SoftMax层的原理图如图所示，输入和输出均为32位宽的10个分类，即32x10=320

![在这里插入图片描述][cd6149b8e9414ddab165ff49adf8db81.png_pic_center]

本项目softmax实现逻辑为：

*  指数计算(通过exponent实现)
 *  计算指数和(通过floatAdd实现)
 *  求指数和倒数(通过floatReciprocal实现)
 *  计算每个元素的softmax值(通过floatMult实现)

## 1.2 exponent ##

每个输入分别输入到各自的exponent模块，计算指数，该模块的输入和输出位宽均为32位，输入1个数，计算输出1个指数

![在这里插入图片描述][541e7f5985664f6c81f346174f50b9df.png_pic_center]

exponent模块展开原理图，如图所示，包含2个乘法器和1个加法器

![在这里插入图片描述][304a3db4b5dd48a985b940bb87782994.png_pic_center]

## 1.3 floatAdd ##

加法器计算所有指数的和

![在这里插入图片描述][127bbcfb042a434f948154966751efca.png_pic_center]

## 1.4 floatReciprocal ##

floatReciprocal模块计算指数和的倒数

![在这里插入图片描述][29815e3dbe974e1a9253529c107988b0.png_pic_center]

floatReciprocal模块展开原理图，如图所示

![在这里插入图片描述][8c82bf9ab74343c98b8e48afd49a9352.png_pic_center]

## 1.5 floatMult ##

乘法器计算各输入的softmax值，然后输出

![在这里插入图片描述][b02136555f3c489d8f993f09316472f3.png_pic_center]

# 2 代码实现 #

## 2.1 floatAdd ##

### 2.1.1 设计输入 ###

创建floatAdd文件，操作如图：  
![在这里插入图片描述][bda3528d92af46309f195109a7c0d239.png_pic_center]

输入文件名：

![在这里插入图片描述][3ac8a7ca15914a80885c95a25bf6868d.png_pic_center]

双击打开，输入代码：

module floatAdd (floatA,floatB,sum);
    	
    input [31:0] floatA, floatB;
    output reg [31:0] sum;
    
    reg sign;
    reg [7:0] exponent;
    reg [22:0] mantissa;
    reg [7:0] exponentA, exponentB;
    reg [23:0] fractionA, fractionB, fraction;	//fraction = {1,mantissa}
    reg [7:0] shiftAmount;
    reg cout;
    
    always @ (floatA or floatB) begin
    	exponentA = floatA[30:23];
    	exponentB = floatB[30:23];
    	fractionA = {
        1'b1,floatA[22:0]};
    	fractionB = {
        1'b1,floatB[22:0]}; 
    	
    	exponent = exponentA;
    
    	if (floatA == 0) begin						//special case (floatA = 0)
    		sum = floatB;
    	end else if (floatB == 0) begin					//special case (floatB = 0)
    		sum = floatA;
    	end else if (floatA[30:0] == floatB[30:0] && floatA[31]^floatB[31]==1'b1) begin
    		sum=0;
    	end else begin
    		if (exponentB > exponentA) begin
    			shiftAmount = exponentB - exponentA;
    			fractionA = fractionA >> (shiftAmount);
    			exponent = exponentB;
    		end else if (exponentA > exponentB) begin 
    			shiftAmount = exponentA - exponentB;
    			fractionB = fractionB >> (shiftAmount);
    			exponent = exponentA;
    		end
    		if (floatA[31] == floatB[31]) begin			//same sign
    			{
        cout,fraction} = fractionA + fractionB;
    			if (cout == 1'b1) begin
    				{
        cout,fraction} = {
        cout,fraction} >> 1;
    				exponent = exponent + 1;
    			end
    			sign = floatA[31];
    		end else begin						//different signs
    			if (floatA[31] == 1'b1) begin
    				{
        cout,fraction} = fractionB - fractionA;
    			end else begin
    				{
        cout,fraction} = fractionA - fractionB;
    			end
    			sign = cout;
    			if (cout == 1'b1) begin
    				fraction = -fraction;
    			end else begin
    			end
    			if (fraction [23] == 0) begin
    				if (fraction[22] == 1'b1) begin
    					fraction = fraction << 1;
    					exponent = exponent - 1;
    				end else if (fraction[21] == 1'b1) begin
    					fraction = fraction << 2;
    					exponent = exponent - 2;
    				end else if (fraction[20] == 1'b1) begin
    					fraction = fraction << 3;
    					exponent = exponent - 3;
    				end else if (fraction[19] == 1'b1) begin
    					fraction = fraction << 4;
    					exponent = exponent - 4;
    				end else if (fraction[18] == 1'b1) begin
    					fraction = fraction << 5;
    					exponent = exponent - 5;
    				end else if (fraction[17] == 1'b1) begin
    					fraction = fraction << 6;
    					exponent = exponent - 6;
    				end else if (fraction[16] == 1'b1) begin
    					fraction = fraction << 7;
    					exponent = exponent - 7;
    				end else if (fraction[15] == 1'b1) begin
    					fraction = fraction << 8;
    					exponent = exponent - 8;
    				end else if (fraction[14] == 1'b1) begin
    					fraction = fraction << 9;
    					exponent = exponent - 9;
    				end else if (fraction[13] == 1'b1) begin
    					fraction = fraction << 10;
    					exponent = exponent - 10;
    				end else if (fraction[12] == 1'b1) begin
    					fraction = fraction << 11;
    					exponent = exponent - 11;
    				end else if (fraction[11] == 1'b1) begin
    					fraction = fraction << 12;
    					exponent = exponent - 12;
    				end else if (fraction[10] == 1'b1) begin
    					fraction = fraction << 13;
    					exponent = exponent - 13;
    				end else if (fraction[9] == 1'b1) begin
    					fraction = fraction << 14;
    					exponent = exponent - 14;
    				end else if (fraction[8] == 1'b1) begin
    					fraction = fraction << 15;
    					exponent = exponent - 15;
    				end else if (fraction[7] == 1'b1) begin
    					fraction = fraction << 16;
    					exponent = exponent - 16;
    				end else if (fraction[6] == 1'b1) begin
    					fraction = fraction << 17;
    					exponent = exponent - 17;
    				end else if (fraction[5] == 1'b1) begin
    					fraction = fraction << 18;
    					exponent = exponent - 18;
    				end else if (fraction[4] == 1'b1) begin
    					fraction = fraction << 19;
    					exponent = exponent - 19;
    				end else if (fraction[3] == 1'b1) begin
    					fraction = fraction << 20;
    					exponent = exponent - 20;
    				end else if (fraction[2] == 1'b1) begin
    					fraction = fraction << 21;
    					exponent = exponent - 21;
    				end else if (fraction[1] == 1'b1) begin
    					fraction = fraction << 22;
    					exponent = exponent - 22;
    				end else if (fraction[0] == 1'b1) begin
    					fraction = fraction << 23;
    					exponent = exponent - 23;
    				end
    			end
    		end
    		mantissa = fraction[22:0];
    		sum = {
        sign,exponent,mantissa};			
    	end		
    end
    
    endmodule

如图所示：

![在这里插入图片描述][216a6ad5b43b480280f8def6cbf7603e.png_pic_center]

### 2.1.2 分析与综合 ###

将floatAdd设置为顶层：

![在这里插入图片描述][ced29e25e1f0487395f48ac984e113b8.png_pic_center]

对设计进行分析，操作如图：

![在这里插入图片描述][203843290c5240afaf9a24e40f7a8c79.png_pic_center]

分析后的设计，Vivado自动生成原理图，如图：

![在这里插入图片描述][2735c4b1a81c4dd69b38aab8235eff49.png_pic_center]

对设计进行综合，操作如图：

![在这里插入图片描述][a2d48bbb32db45dfb692698d7bc84c46.png_pic_center]

综合完成，关闭即可：

![在这里插入图片描述][26eac6e42de94ff0b42fa70ff21101ce.png_pic_center]

### 2.1.3 功能仿真 ###

创建仿真激励文件，操作如图：

![在这里插入图片描述][119fb8e31d6243128db8117d81f18467.png_pic_center]

输入激励文件名：

![在这里插入图片描述][17d2f19743474a21966e5c63810c86a8.png_pic_center]

确认创建：

![在这里插入图片描述][aebb4922b7814fa5a73a3b026eeea651.png_pic_center]

双击打开，输入激励代码：

`timescale 1ns / 1ps
    
    module tb_floatAdd();
    reg [31:0] floatA;
    reg [31:0] floatB;
    wire [31:0] sum;
    
    initial begin
    	
    	// 0.0004125 + 0.000000525
    	#0
    	floatA = 32'hbab1cf4b;
    	floatB = 32'h3aaaad74;
    
    	// 0.0004125 + 0
    	#10
    	floatA = 32'b00111001110110000100010011010000;
    	floatB = 32'b00000000000000000000000000000000;
    
    	#10
    	$stop;
    end
    
    floatAdd FADD
    (
    	.floatA(floatA),
    	.floatB(floatB),
    	.sum(sum)
    );
    
    endmodule

如图所示：

![在这里插入图片描述][dca0d0f0e0e34d8195f80ce2909297d6.png_pic_center]

将tb\_floatAdd设置为顶层：

![在这里插入图片描述][d1a41fe587c447c7bb0841f8f5b454f3.png_pic_center]

开始进行仿真，操作如下：

![在这里插入图片描述][fb195ef4e8b342cda8731521cf5f288d.png_pic_center]

仿真波形，如图：

![在这里插入图片描述][34d13800d62441c5b1fc8911d7522652.png_pic_center]  
仿真结束，关闭仿真：

![在这里插入图片描述][4947c4f89d4e4ed489cce596263f871c.png_pic_center]

## 2.2 floatMult ##

### 2.2.1 设计输入 ###

创建floatMult文件，操作如图：

![在这里插入图片描述][c28413d773014768a221e0d2c8e07e9c.png_pic_center]  
双击打开，输入代码：

module floatMult (floatA,floatB,product);
    
    input [31:0] floatA, floatB;
    output reg [31:0] product;
    
    reg sign;
    reg [7:0] exponent;
    reg [22:0] mantissa;
    reg [23:0] fractionA, fractionB;	//fraction = {1,mantissa}
    reg [47:0] fraction;
    
    always @ (floatA or floatB) begin
    	if (floatA == 0 || floatB == 0) begin
    		product = 0;
    	end else begin
    		sign = floatA[31] ^ floatB[31];
    		exponent = floatA[30:23] + floatB[30:23] - 8'd127 + 8'd2;
    	
    		fractionA = {
        1'b1,floatA[22:0]};
    		fractionB = {
        1'b1,floatB[22:0]};
    		fraction = fractionA * fractionB;
    		
    		if (fraction[47] == 1'b1) begin
    			fraction = fraction << 1;
    			exponent = exponent - 1; 
    		end else if (fraction[46] == 1'b1) begin
    			fraction = fraction << 2;
    			exponent = exponent - 2;
    		end else if (fraction[45] == 1'b1) begin
    			fraction = fraction << 3;
    			exponent = exponent - 3;
    		end else if (fraction[44] == 1'b1) begin
    			fraction = fraction << 4;
    			exponent = exponent - 4;
    		end else if (fraction[43] == 1'b1) begin
    			fraction = fraction << 5;
    			exponent = exponent - 5;
    		end else if (fraction[42] == 1'b1) begin
    			fraction = fraction << 6;
    			exponent = exponent - 6;
    		end else if (fraction[41] == 1'b1) begin
    			fraction = fraction << 7;
    			exponent = exponent - 7;
    		end else if (fraction[40] == 1'b1) begin
    			fraction = fraction << 8;
    			exponent = exponent - 8;
    		end else if (fraction[39] == 1'b1) begin
    			fraction = fraction << 9;
    			exponent = exponent - 9;
    		end else if (fraction[38] == 1'b0) begin
    			fraction = fraction << 10;
    			exponent = exponent - 10;
    		end else if (fraction[37] == 1'b1) begin
    			fraction = fraction << 11;
    			exponent = exponent - 11;
    		end else if (fraction[36] == 1'b1) begin
    			fraction = fraction << 12;
    			exponent = exponent - 12;
    		end else if (fraction[35] == 1'b1) begin
    			fraction = fraction << 13;
    			exponent = exponent - 13;
    		end else if (fraction[34] == 1'b1) begin
    			fraction = fraction << 14;
    			exponent = exponent - 14;
    		end else if (fraction[33] == 1'b1) begin
    			fraction = fraction << 15;
    			exponent = exponent - 15;
    		end else if (fraction[32] == 1'b1) begin
    			fraction = fraction << 16;
    			exponent = exponent - 16;
    		end else if (fraction[31] == 1'b1) begin
    			fraction = fraction << 17;
    			exponent = exponent - 17;
    		end else if (fraction[30] == 1'b1) begin
    			fraction = fraction << 18;
    			exponent = exponent - 18;
    		end else if (fraction[29] == 1'b0) begin
    			fraction = fraction << 19;
    			exponent = exponent - 19;
    		end else if (fraction[28] == 1'b1) begin
    			fraction = fraction << 20;
    			exponent = exponent - 20;
    		end else if (fraction[27] == 1'b1) begin
    			fraction = fraction << 21;
    			exponent = exponent - 21;
    		end else if (fraction[26] == 1'b1) begin
    			fraction = fraction << 22;
    			exponent = exponent - 22;
    		end else if (fraction[27] == 1'b1) begin
    			fraction = fraction << 23;
    			exponent = exponent - 23;
    		end
    	
    		mantissa = fraction[47:25];
    		product = {
        sign,exponent,mantissa};
    	end
    end
    
    endmodule

如图所示：

![在这里插入图片描述][e87821b5445f41b3a14210db61488c47.png_pic_center]

### 2.2.2 分析与综合 ###

将floatMult设置为顶层：

![在这里插入图片描述][ccaf784d353e4449abef19c0dab6b9ce.png_pic_center]

关闭上次的分析文件：

![在这里插入图片描述][ac54061e0c5f4ef684c4399d8fb92945.png_pic_center]

对设计进行分析，操作如图：

![在这里插入图片描述][6683a93d2fc44bc990796962870ba68c.png_pic_center]

分析后的设计，Vivado自动生成原理图，如图：

![在这里插入图片描述][b6cf7a0b9e0c453d84ed4c0ec7a3da95.png_pic_center]

对设计进行综合，综合完成，关闭即可：

![在这里插入图片描述][246b8976725e4da1a5df0985c20c02e5.png_pic_center]

### 2.2.3 功能仿真 ###

创建激励文件tb\_floatMult：

![在这里插入图片描述][6c5ea69075484e90bd04980d74c6b916.png_pic_center]

双击打开，输入激励：

`timescale 1ns / 1ps
    
    module tb_floatMult();
    reg [31:0] floatA;
    reg [31:0] floatB;
    wire [31:0] product;
    
    initial begin
    	
    	// 0.0004125 * 0.000000525
    	#0
    	floatA = 32'b00111001110110000100010011010000;
    	floatB = 32'b00110101000011001110110110111010;
    
    	// 0.0004125 * 0
    	#10
    	floatA = 32'b00111001110110000100010011010000;
    	floatB = 32'b00000000000000000000000000000000;
    
    	#10
    	$stop;
    end
    
    floatMult FM
    (
    	.floatA(floatA),
    	.floatB(floatB),
    	.product(product)
    );
    
    endmodule

如图所示：

![在这里插入图片描述][48efb462f5ad483d8217328f75c67f87.png_pic_center]

将tb\_floatMult设置为顶层：

![在这里插入图片描述][a1d8bcea34624b2da88b61e7d3595857.png_pic_center]

开始进行仿真：

![在这里插入图片描述][92724b82436744dbbb8d7ff4d92036f9.png_pic_center]

仿真波形如图：

![在这里插入图片描述][83e882149a204493a82acfe53f0d2dc5.png_pic_center]

仿真结束，关闭仿真：

![在这里插入图片描述][5d5b19a648ac4b55b776238aff61284a.png_pic_center]

## 2.3 exponent ##

### 2.3.1 设计输入 ###

创建exponent文件，如图：

![在这里插入图片描述][6b7ae72cb7c24102b9f483919fd417cd.png_pic_center]

双击打开，输入代码：

module exponent (x,clk,enable,output_exp,ack);
    parameter DATA_WIDTH=32;
    localparam taylor_iter=7;
    input [DATA_WIDTH-1:0] x;
    input clk;
    input enable;
    output reg ack;
    output reg [DATA_WIDTH-1:0] output_exp;
    
    reg [DATA_WIDTH*taylor_iter-1:0] divisors; // 1/6 1/5 1/4 1/3 1/2 1 1
    reg [DATA_WIDTH-1:0] mult1; //is 1 in the first cycle and then the output of the second multiplication in the rest
    reg [DATA_WIDTH-1:0] one_or_x; //one in the first cycle and then x for the rest
    wire [DATA_WIDTH-1:0] out_m1; //output of the first multiplication which is either with 1 or x
    wire [DATA_WIDTH-1:0] out_m2; //the output of the second muliplication and the input of the first
    wire [DATA_WIDTH-1:0] output_add1;
    reg [DATA_WIDTH-1:0] out_reg; //the output of the Addition each cycle 
    
    floatMult FM1 (mult1,one_or_x,out_m1); 
    floatMult FM2 (out_m1,divisors[31:0],out_m2); 
    floatAdd FADD1 (out_m2,out_reg,output_add1); 
    
    always @ (posedge clk) begin
        if(enable==1'b0) begin
            one_or_x=32'b00111111100000000000000000000000; //initially 1
            mult1=32'b00111111100000000000000000000000; //initially 1
            out_reg=32'b00000000000000000000000000000000; //initially 0
            output_exp=32'b00000000000000000000000000000000; //output zero until ack is 1
            divisors=224'b00111110001010101010101010101011_00111110010011001100110011001101_00111110100000000000000000000000_00111110101010101010101010101011_00111111000000000000000000000000_00111111100000000000000000000000_00111111100000000000000000000000;
            ack=1'b0; // acknowledge is 0 at the beginning
        end 
        else begin
    	   one_or_x=x;
    	   mult1=out_m2; //get the output of the second multiplication to multiply with x
    	   divisors=divisors>>32; //shift 32 bit to divide the out_m1 with the new number to compute the factorial
    	   out_reg=output_add1;
    	   if(divisors==224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000) 
    	   begin
    		  output_exp=output_add1;
    		  ack=1'b1;
    	   end
    	  end
    end
    
    endmodule

如图所示：

![在这里插入图片描述][abe6af0f2e3a4fb18c63fe50935b34a5.png_pic_center]

### 2.3.2 分析与综合 ###

将exponent文件设置为顶层：

![在这里插入图片描述][3161013ba5cf4180978a0935864d9a48.png_pic_center]

关闭上次的分析文件：

![在这里插入图片描述][490092c225684556b81c3237cc0d21b4.png_pic_center]

对本次设计进行分析，操作如图：

![在这里插入图片描述][a7f79c2ba1f9445d94b2ac037851b175.png_pic_center]

分析后的设计，Vivado自动生成原理图，如图：

![在这里插入图片描述][d17bf195d8b04751943bccdbe0608947.png_pic_center]  
对设计进行综合，操作如图：

![在这里插入图片描述][e3a198724481467e800ec638e31b05b2.png_pic_center]

综合完成，关闭即可：

![在这里插入图片描述][2249f9adab244663a05d2c58456bd5cd.png_pic_center]

### 2.3.3 功能仿真 ###

创建TestBench，操作如图所示：

![在这里插入图片描述][44cf7da305b3404cb194511f6062a4ea.png_pic_center]  
双击打开，输入激励代码：

`timescale 1ns / 1ps
    
    module tb_exponent();
    localparam DATA_WIDTH=32;
    reg [DATA_WIDTH-1:0] x;
    reg clk;
    reg enable;
    wire [DATA_WIDTH-1:0] output_exp;
    wire ack; 
    exponent #(.DATA_WIDTH(DATA_WIDTH)) exp (.x(x),.clk(clk),.output_exp(output_exp),.ack(ack),.enable(enable));
    
    localparam PERIOD = 100;
    always 
    	#(PERIOD/2) clk = ~clk;
    
    initial begin
    	clk=1'b1;
    	x=32'b00111111010101100110110011110100; //0.8376
    	enable=1'b0;
    	#(PERIOD);
    	enable=1'b1;
    	while (ack!=1'b1) begin //7 clock cycles to finish
    		#(PERIOD);
    	end
    	//output is 2.31074953079 and real should be 2.310814361840001 
    	x=32'b10111111011101011100001010001111; //-0.96
    	enable=1'b0;
       	#(PERIOD);
       	enable=1'b1;
        	while (ack!=1'b1) begin //7 clock cycles to finish
            	#(PERIOD);
        	end
    	//output is 0.383025914431 and real should be 0.38289288597511206
    end
    
    endmodule

如图所示：

![在这里插入图片描述][327de06465d2407c85d35274e98dfc9f.png_pic_center]

将tb\_exponent设置为顶层：

![在这里插入图片描述][48427dc2fb9e4210b475455d3fa06584.png_pic_center]

开始进行仿真，操作如图：

![在这里插入图片描述][04607bc394d442dcb0424b0d425ae374.png_pic_center]

仿真波形，如图：

![在这里插入图片描述][090511c0b4724324940032a6892942d0.png_pic_center]

仿真完成，关闭：

![在这里插入图片描述][43d01614cc8b4df2bd49ca01bff452f4.png_pic_center]

## 2.4 floatReciprocal ##

### 2.4.1 设计输入 ###

创建floatReciprocal文件，如图：

![在这里插入图片描述][cb45f587ae3c46bfb5c4edb06221baa4.png_pic_center]

双击打开，输入代码：

module floatReciprocal(number,enable,clk,output_rec,ack);
    
    parameter DATA_WIDTH=32;
    input [DATA_WIDTH-1:0] number; //the number that we need to get the 1/number of
    input clk,enable; 
    output reg[DATA_WIDTH-1:0] output_rec; // = 1/number
    output reg ack;
    
    wire [DATA_WIDTH-1:0] Ddash; // D' = Mantissa of D and exponent of -1
    wire [DATA_WIDTH-1:0] P2Ddash; // (-32/17) * D'
    wire [DATA_WIDTH-1:0] Xi ; // X[i]= 43/17 - (32/17)D'
    wire [DATA_WIDTH-1:0] Xip1; //X[i+1]
    wire [DATA_WIDTH-1:0] out0; // Xi*D
    wire [DATA_WIDTH-1:0] out1; // 1-Xi*D
    wire [DATA_WIDTH-1:0] out2; // X*(1-Xi*D)
    reg  [DATA_WIDTH-1:0] mux;
    
    localparam P1=32'b01000000001101001011010010110101; // 43/17
    localparam P2=32'b10111111111100001111000011110001; // -32/17
    
    assign Ddash={
        {
        1'b0,8'b01111110},number[22:0]};
    
    floatMult FM1 (P2,Ddash,P2Ddash); // -(32/17)* D'
    floatAdd FADD1 (P2Ddash,P1,Xi); // 43/17 * (-32/17)D'
    floatMult FM2 (mux,Ddash,out0); // Xi*D'
    floatAdd FSUB1 (32'b00111111100000000000000000000000,{
        1'b1,out0[DATA_WIDTH-2:0]},out1); // 1-Xi*D
    floatMult FM3 (mux,out1,out2); // X*(1-Xi*D)
    floatAdd FADD2 (mux,out2,Xip1); //Xi+Xi*(1-D*Xi)
    
    /*always @(number) begin
    	//when a new input is entered the ack signal is reset and the mux is Xi
    	ack=1'b0; //reset finish bit
    	reset=1'b1;
    end*/
    
    
    always @ (negedge clk) begin
    	if (enable==1'b0) begin
    		mux=Xi;
    		ack=1'b0;
    	end
    	else begin 
    		if(mux==Xip1) begin
    			ack=1'b1; //set ack bit to show that the division is done
    			output_rec={
        {
        number[31],8'b11111101-number[30:23]},Xip1[22:0]}; //sign of number, new exponent, mantissa of Xip1
    		end 
    		else begin
    			mux=Xip1; //continue until ack is 1
    		end
    	end
    	
    end
    
    endmodule

如图所示：

![在这里插入图片描述][7ab83b857f984f829d28e7e167d273ca.png_pic_center]

### 2.4.2 分析与综合 ###

将floatReciprocal文件设置为顶层：

![在这里插入图片描述][f475079a9e234eb282beb497c0788a6a.png_pic_center]

关闭上次的分析文件：

![在这里插入图片描述][df1cdb54cc014952bef94d97ab157bb6.png_pic_center]

对设计进行分析，操作如图：

![在这里插入图片描述][c0b2e2beec19497a93d24d9724b0729c.png_pic_center]

分析后的设计，Vivado自动生成原理图，如图：

![在这里插入图片描述][5b1622d198f64dfbaf63e2e8f3522db5.png_pic_center]

对设计进行综合，操作如图：

![在这里插入图片描述][67d41e4b46d8465680f6a098378d1a9a.png_pic_center]

综合完成，关闭：

![在这里插入图片描述][0497bb51bcdf4095844d0f5fdbd3409a.png_pic_center]

### 2.4.3 功能仿真 ###

创建tb\_floatReciprocal激励文件：

![在这里插入图片描述][68d696bd70ec44bfac59bc67a530dfbb.png_pic_center]

双击打开，输入激励代码：

`timescale 1ns / 1ps
    
    module tb_floatReciprocal();
    localparam DATA_WIDTH=32;
    reg [DATA_WIDTH-1:0] num;
    reg clk,enable;
    wire [DATA_WIDTH-1:0] output_rec;
    wire ack;
    
    floatReciprocal #(.DATA_WIDTH(DATA_WIDTH))  FA (.number(num),.clk(clk),.output_rec(output_rec),.ack(ack),.enable(enable));
    
    localparam PERIOD = 100;
    
    always 
    	#(PERIOD/2) clk = ~clk;
    
    
    initial begin
    	clk=1'b1; //positive edge first
    	num=32'b00111110101100001010001111010111; //0.345
    	enable=1'b0;
    	#(PERIOD);
    	enable=1'b1;
    	while( ack!=1'b1) begin
    		#(PERIOD);
    	end
    	//output is 2.89855074883
    	num=32'b10111110111111101111100111011011;
    	enable=1'b0;
    	#(PERIOD);
    	enable=1'b1; 
    	while (ack!=1'b1) begin
    		#(PERIOD);
    	end
    	//output is -2.00803232193
    	$stop;
    end
    
    endmodule

如图所示：

![在这里插入图片描述][af532783d71e44c691e4fa60f76871d8.png_pic_center]  
将tb\_floatReciprocal设置为顶层：

![在这里插入图片描述][b62b7ab443d348ce92bb37116a2b63d0.png_pic_center]

开始进行仿真，操作如图：

![在这里插入图片描述][b0eef8c127f1441fbd1515751ee6597d.png_pic_center]

仿真波形，如图：

![在这里插入图片描述][9888edb05f4f4354986e7da946721651.png_pic_center]

仿真结束，关闭仿真：

![在这里插入图片描述][85c89f780cd3440fa57a2b3bf23daeda.png_pic_center]

## 2.5 softmax ##

### 2.5.1 设计输入 ###

创建softmax文件，如图：

![在这里插入图片描述][d05b18b124b342228eba104f9a86f7f9.png_pic_center]  
双击打开，输入代码：

module softmax(inputs,clk,enable,outputs,ackSoft);
    parameter DATA_WIDTH=32;
    localparam inputNum=10;
    input [DATA_WIDTH*inputNum-1:0] inputs;
    input clk;
    input enable;
    output reg [DATA_WIDTH*inputNum-1:0] outputs;
    output reg ackSoft;
    
    wire [DATA_WIDTH-1:0] expSum;
    wire [DATA_WIDTH-1:0] expReciprocal;
    wire [DATA_WIDTH-1:0] outMul;
    wire [DATA_WIDTH*inputNum-1:0] exponents ;
    wire [inputNum-1:0] acksExp; //acknowledge signals of exponents 
    wire ackDiv; //ack signal of the division unit
    
    reg enableDiv; //signal to enable division unit initially zero
    reg [DATA_WIDTH-1:0] outExpReg;
    reg [3:0] mulCounter;
    reg [3:0] addCounter;
    
    genvar i;
    generate
    	for (i = 0; i < inputNum; i = i + 1) begin
    		exponent #(.DATA_WIDTH(DATA_WIDTH)) exp (
    		.x(inputs[DATA_WIDTH*i+:DATA_WIDTH]),
    		.enable(enable),
    		.clk(clk),
    		.output_exp(exponents[DATA_WIDTH*i+:DATA_WIDTH]),
    		.ack(acksExp[i]));
    	end
    endgenerate
    
    floatAdd FADD1 (exponents[DATA_WIDTH*addCounter+:DATA_WIDTH],outExpReg,expSum);
    floatReciprocal #(.DATA_WIDTH(DATA_WIDTH)) FR (.number(expSum),.clk(clk),.output_rec(expReciprocal),.ack(ackDiv),.enable(enableDiv));
    floatMult FM1 (exponents[DATA_WIDTH*mulCounter+:DATA_WIDTH],expReciprocal,outMul); //multiplication with reciprocal
    
    always @ (negedge clk) begin
    	if(enable==1'b1) begin
    		if(ackSoft==1'b0) begin 
    			if(acksExp[0]==1'b1) begin //if the exponents finished
    				if(enableDiv==1'b0) begin //division still did not start
    					if(addCounter<4'b1001) begin
    						addCounter=addCounter+1;
    						outExpReg=expSum;
    					end
    					else begin
    						enableDiv=1'b1;
    					end
    				end
    				else if(ackDiv==1'b1) begin //check if the reciprocal is ready
    					if(mulCounter<4'b1010) begin
    						outputs[DATA_WIDTH*mulCounter+:DATA_WIDTH]=outMul;
    						mulCounter=mulCounter+1;
    					end
    					else begin
    						ackSoft=1'b1;
    					end
    				end
    			end
    		end
    	end
    	else begin
    		//if enable is off reset all counters and acks
    		mulCounter=4'b0000;
    		addCounter=4'b0000;
    		outExpReg=32'b00000000000000000000000000000000;
    		ackSoft=1'b0;
    		enableDiv=1'b0;
    	end
    	
    end
    
    endmodule

如图所示：

![在这里插入图片描述][3b44585b349f4a26a67a55537af253bb.png_pic_center]

### 2.5.2 分析与综合 ###

将softmax文件设置为顶层：

![在这里插入图片描述][94a25b0a5b9449e79158e27dd14223f2.png_pic_center]

关闭上次的分析，操作如图：

![在这里插入图片描述][d1a83ec32a824e5abd715f204fdda834.png_pic_center]

对设计进行分析，如图：

![在这里插入图片描述][ffe5c06527df45b19d9b37c1cbec9ba5.png_pic_center]

分析后的设计，Vivado自动生成原理图，如图：

![在这里插入图片描述][a309d90430544da7ba320aae55a409e8.png_pic_center]

对设计进行综合，操作如图：

![在这里插入图片描述][fa844b38235446fe87e0617134c61a71.png_pic_center]

### 2.5.3 功能仿真 ###

创建tb\_softmax文件，如图：

![在这里插入图片描述][64ed8d4bebfa46c68c05853eb60ce85c.png_pic_center]  
双击打开，输入激励代码：

`timescale 1ns / 1ps
    
    module tb_softmax();
    localparam DATA_WIDTH=32;
    localparam inputNum=10;
    reg [DATA_WIDTH*inputNum-1:0] inputs;
    reg clk;
    reg enable;
    wire [DATA_WIDTH*inputNum-1:0] outputs;
    wire ackSoft;
    softmax #(.DATA_WIDTH(DATA_WIDTH)) soft(inputs,clk,enable,outputs,ackSoft);
    
    localparam PERIOD = 100;
    integer count;
    always 
    	#(PERIOD/2) clk = ~clk;
    
    initial begin
    	clk=1'b1;
    	inputs=320'b00111110010011001100110011001101_10111110010011001100110011001101_00111111100110011001100110011010_00111111101001100110011001100110_10111111011001100110011001100110_00111110100110011001100110011010_01000000010001100110011001100110_10111100101000111101011100001010_00111111100011100001010001111011_00111110101001010110000001000010;
    	//inputs are 0.2 -0.2 1.2 1.3 -0.9 0.3 3.1 -0.02 1.11 0.323
    	count=1;
    	enable=1'b0;
    	#(PERIOD);
    	enable=1'b1;
    	
    	while(ackSoft!=1'b1) begin
    		count=count+1;
    		#(PERIOD);		
    	end
    	//outputs are 0.03255, 0.02182, 0.08847, 0.09776, 0.0108, 0.0359, 0.5687,  0.02612, 0.0808, 0.03681
    
    	inputs=320'b00111111001100001010001111010111_10111110010011001100110011001101_00111111100110011001100110011010_00111111101001100110011001100110_10111111011001100110011001100110_00111110100110011001100110011010_01000000010001100110011001100110_10111100101000111101011100001010_00111111100011100001010001111011_00111110101001010110000001000010;
    	//inputs are 0.69 -0.2 1.2 1.3 -0.9 0.3 3.1 -0.02 1.11 0.323
    	count=1;
    	enable=1'b0;
    	#(PERIOD);
    	enable=1'b1;
    	while(ackSoft!=1'b1) begin
    		count=count+1;
    		#(PERIOD);
    
    	end
    	//outputs are 0.05207118 0.0213835  0.0866926  0.09579553 0.01062096 0.03525543 0.5572659  0.0256007  0.07923851 0.0360757
     										
    end
    endmodule

如图所示：

![在这里插入图片描述][6bc343d400694d66aa46ef3e8ce234c6.png_pic_center]

将tb\_softmax文件设置为顶层：

![在这里插入图片描述][3c5d74d2110044e38fb3a3ec8460d360.png_pic_center]

开始进行仿真，如图：

![在这里插入图片描述][de2b50435b354139a356a7fe68f29ea5.png_pic_center]

仿真波形：

![在这里插入图片描述][1af759bd53d54d7a93a9353077b2d431.png_pic_center]

仿真结束，关闭：

![在这里插入图片描述][44a10f66f62c4ef98ce8b43385bf2319.png_pic_center]

## 2.6 integrationFC ##

### 2.6.1 设计输入 ###

创建integrationFC文件，操作如图：

![在这里插入图片描述][b1b4021a18e5418c9d870255e6ec8038.png_pic_center]  
双击打开，输入代码：

module integrationFC(clk,reset,iFCinput,CNNoutput);
    
    parameter DATA_WIDTH = 32;
    parameter IntIn = 120;
    parameter FC_1_out = 84;
    parameter FC_2_out = 10;
    
    input clk, reset;
    input [IntIn*DATA_WIDTH-1:0] iFCinput;
    output [FC_2_out*DATA_WIDTH-1:0] CNNoutput;
    
    wire [FC_1_out*DATA_WIDTH-1:0] fc1Out;
    wire [FC_1_out*DATA_WIDTH-1:0] fc1OutTanh;
    
    wire [FC_2_out*DATA_WIDTH-1:0] fc2Out;
    wire [FC_2_out*DATA_WIDTH-1:0] fc2OutSMax;
    
    reg SMaxEnable;
    wire DoneFlag;
    
        
    softmax SMax(
          .inputs(fc2Out),
          .clk(clk),
          .enable(SMaxEnable),
          .outputs(CNNoutput),
          .ackSoft(DoneFlag)
          );
          
    endmodule

如图所示：

![在这里插入图片描述][e1d8e8a4f94e4cf9823952967ddfde3c.png_pic_center]

### 2.6.2 分析与综合 ###

将integrationFC设置为顶层：

![在这里插入图片描述][14e50f459e4942afaf4fc2bdde1fa798.png_pic_center]

关闭上次的分析文件：

![在这里插入图片描述][9af6a58685754cc59490cfe96156686f.png_pic_center]

对设计进行分析，操作如图：

![在这里插入图片描述][57553c997fec4101b6e73c506418a474.png_pic_center]

分析后的设计，Vivado生成原理图：

![在这里插入图片描述][5aac6c51ee584069b5f4febc99840711.png_pic_center]

**希望本文对大家有帮助，上文若有不妥之处，欢迎指正**

**分享决定高度，学习拉开差距**

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