逻辑门逻辑_逻辑门

偏执的太偏执、 2023-03-05 07:28 23阅读 0赞

逻辑门逻辑

**Logic Gates** are the fundamental building blocks of a digital system. The name Logic Gates has been derived from the fact that the device should be able to make decisions on its own. It should be able to distinguish different output levels, for example, one output level is produced when some level of input is present and other output level is produced when another set of input is provided.

**逻辑门**是数字系统的基本构建块。 逻辑门之所以得名，是因为该设备应该能够自行做出决定。 它应该能够区分不同的输出级别，例如，当某个输入级别存在时，将生成一个输出级别，而当提供另一组输入时，则将生成另一个输出级别。

Input and Output of logic gates occur in only two states either ON/High/True or OFF/Low/False. We simply represent these in numerical form as 1 and 0 respectively.

逻辑门的输入和输出仅在两种状态下出现：ON / High / True或OFF / Low / False。 我们仅将它们分别以数字形式表示为1和0。

A Truth Table contains all possible combinations of inputs and their possible outputs. It shows how the logic circuit's output responds to various combinations of logic levels at the inputs.

真值表包含输入及其所有可能输出的所有可能组合。 它显示了逻辑电路的输出如何响应输入端逻辑电平的各种组合。

There are just three basic types of gates - **AND Gate**, **OR Gate**, and **NOT Gate**. Additionally, we have two more gates namely, **XOR Gate** and **XNOR Gate**.

闸门只有三种基本类型-AND **门** ， **OR门**和**NOT门** 。 另外，我们还有两个门，即**XOR Gate**和**XNOR Gate** 。

### 1)与门 **(**1) AND Gate**)** ###

An **AND Gate** may have two or more inputs. The output of **AND Gate** will be 1 when all of its inputs are in state 1. The output will be in 0 states if even any one of its inputs is in state 0. Logic operation of **AND Gate** is given as **Y= A.B**.

**与门**可能有两个或更多输入。 当其所有输入都处于状态1时， **与门**的输出将为1。即使其输入中的任何一个处于状态0，其输出也将处于0状态。 **与门的**逻辑运算为**Y = AB** 。

**Symbol and Truth table for AND Gate:**

**AND门的符号和真值表：**

![AND Gate][]

### 2)或门 **(**2) OR Gate**)** ###

An **OR Gate** may also have two or more inputs. The output of **OR Gate** will be 1 when any of its inputs are in state 1. The output will be in 0 state, if all of its inputs are in state 0. Logic operation of **OR Gate** is given as **Y = A+B**.

**或门**也可能具有两个或多个输入。 当其任何输入的状态均为1时， **或门**的输出将为1。如果其所有输入的状态均为0，则其输出将为0。 **或门的**逻辑运算为**Y = A + B。**

![OR Gate][]

### 3)非门 **(**3) NOT Gate**)** ###

A **NOT Gate** is used for complementing the input provided. If the input will be high then output will be low and vice-versa. Logic operation of **NOT Gate** is given as: **Y=A'/A** (provided A is the input) which is read as A compliment.

**NOT门**用于补充提供的输入。 如果输入为高，则输出为低，反之亦然。 **NOT Gate的**逻辑运算为： **Y = A'/ A** (假设A为输入)，被读为A补语。

**Symbol and Truth table for NOT Gate:**

**NOT Gate的符号和真值表：**

![NOT Gate][]

### 4)异或门/ XOR门 **(**4) Exclusive-Or Gate/XOR Gate**)** ###

An **XOR Gate** has two inputs. The output of **XOR Gate** will be 1 when and only one of its inputs is provided high state (1). The output will be in 0 state, if both of its inputs are in logic state 0 or logic state 1. Logic operation of **XOR Gate** is given as: **Y= AB + AB = A⊕B**.

**XOR门**具有两个输入。 当**XOR门**的输入只有一个处于高电平状态(1)时，其输出将为1。 如果输出的两个输入都处于逻辑状态0或逻辑状态1，则输出将处于0状态**。XOR门的**逻辑运算如下： **Y = A B + A B = A⊕B** 。

![XOR Gate][]

### 5)异或门/ XNOR门 **(**5) Exclusive-NOR Gate/XNOR Gate**)** ###

An **XNOR Gate** has two inputs. The output of **XNOR Gate** will be 1 when and when both of its inputs are provided either low state (0) or high state (1). The output will be in 0 state, when one of its inputs is in logic state 0 and another in logic state 1. Logic operation of **XNOR Gate** is given as **Y= AB + AB = A⨀B**.

**XNOR门**具有两个输入。 当**XNOR门的**两个输入均处于低电平(0)或高电平(1)时，其输出将为1。 当一个输入的逻辑状态为0且另一个输入的逻辑状态为1时，输出将处于0状态**。XNOR** **门的**逻辑运算为**Y = AB + AB = A⨀B** 。

![XNOR Gate][]

> 翻译自: [https://www.includehelp.com/basics/logic-gates.aspx][https_www.includehelp.com_basics_logic-gates.aspx]

逻辑门逻辑

[AND Gate]: https://www.includehelp.com/basics/Images/AND-Gate.jpg
[OR Gate]: https://www.includehelp.com/basics/Images/OR-Gate.jpg
[NOT Gate]: /images/20230208/d4a5e3f04d76472e993df621da64a40a.png
[XOR Gate]: https://www.includehelp.com/basics/Images/XOR-Gate.jpg
[XNOR Gate]: https://www.includehelp.com/basics/Images/XNOR-Gate.jpg
[https_www.includehelp.com_basics_logic-gates.aspx]: https://www.includehelp.com/basics/logic-gates.aspx