intel/quartus lvds serdes设计问题总结

谁借莪１个温暖的怀抱￠ 2022-12-05 10:28 306阅读 0赞

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70][]

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从手册中可以了解，只要修改.qsf文件中的顺序就可以调整quartus的生成顺序（优先级）。

另外需要注意，高速率低lvds串化因子时时序时难以收敛的，因此优先使用高传化因子8以及tx\_coreclk(而inclock的时序裕量比较低)。

当使用外部pll时似乎不能勾选CPA会导致fiter报错，去掉CPA选项后，tx端信号会有较大变化，rx端信号接口不变。

在生成sof过程中随时查看report信息：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2][]

关于ip的几点说明：

1、使用expll时，CPA不能勾选【fitter会报错】；在工程目录下新建quartus.ini文件如下：【这样就不需要从外部pin来输入时钟，这个时钟在ip配置界面称为"inclock"】

disable_lvds_non_dedicated_refclk_error=on

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3][]

2、pll配置有标准的要求在手册上：而"coreclock"被称为内核时钟就是供内部逻辑使用的时钟

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 5][]

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![20200912175545361.png][]

3、我们期望的连接方式：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 10][]

或者跨多个iobank：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 11][]

4、使用外部PLL时钟时需要注意，LVDS TX/RX ip以及PLL ip同一bank的这三个ip的复位信号需要一致。

同时由于使用coreclock作为内部逻辑时钟，它来自于IOPLL，不能将外部手动复位给到ip复位，而是建议用

nint\_done信号【Reset Release Intel FPGA IP】来复位ip这样可以保证时钟不会复位。

# Reset Release Intel FPGA IP #

<table> 
 <tbody> 
  <tr> 
   <td><strong>Name</strong></td> 
   <td>altera_s10_user_rst_clkgate</td> 
  </tr> 
  <tr> 
   <td><strong>Version</strong></td> 
   <td>19.1.0</td> 
  </tr> 
  <tr> 
   <td><strong>Author</strong></td> 
   <td>Intel Corporation</td> 
  </tr> 
  <tr> 
   <td><strong>Description</strong></td> 
   <td>This IP outputs nINIT_DONE after finishing device initalization. User mode initialization can begin as soon as the nINIT_DONE signal asserts.</td> 
  </tr> 
  <tr> 
   <td><strong>Group</strong></td> 
   <td>Basic Functions/Configuration and Programming</td> 
  </tr> 
 </tbody> 
</table>

## Parameters ##

***No Parameters***

<table> 
 <tbody> 
  <tr> 
   <td colspan="2">This IP has no parameters. The IP has a single output, nINIT_DONE. Refer to the Component Description for more information.</td> 
  </tr> 
 </tbody> 
</table>

## Interfaces ##

***ninit\_done***   -  Conduit

<table> 
 <tbody> 
  <tr> 
   <td colspan="2" style="border-color:#eeeeee;"> <p>&nbsp;</p> </td> 
  </tr> 
  <tr> 
   <td style="border-color:#eeeeee;"><strong>Name</strong></td> 
   <td style="border-color:#eeeeee;"><strong>Role</strong></td> 
   <td style="border-color:#eeeeee;"><strong>Width</strong></td> 
   <td style="border-color:#eeeeee;"><strong>Direction</strong></td> 
   <td style="border-color:#eeeeee;"><strong>Description</strong></td> 
  </tr> 
  <tr> 
   <td style="border-color:#eeeeee;"><strong>ninit_done</strong></td> 
   <td style="border-color:#eeeeee;">ninit_done</td> 
   <td style="border-color:#eeeeee;">1</td> 
   <td style="border-color:#eeeeee;">Output</td> 
   <td style="border-color:#eeeeee;"><em>no description</em></td> 
  </tr> 
 </tbody> 
</table>

[https://www.intel.cn/content/www/cn/zh/programmable/documentation/prh1555609801770.html][https_www.intel.cn_content_www_cn_zh_programmable_documentation_prh1555609801770.html]

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5、intel FPGA 的BUFG：外部输入时钟通过BUFG后再去驱动内部逻辑，同时这个ip具有门控和分频的功能

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 13][]

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主时钟需要添加的约束如下：

![2020091217482669.png][]

6、DPA及Bitslip操作步骤：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 15][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 16][]

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7、关于LVDS的阻抗设置以及电平标准【可以在qsf文件通过约束进行设置】：预加重（默认已使能）/输出电压/端接

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 18][]

这个信息在gpio手册由描述：类似还有iob相关/延时单元设置：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 19][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 20][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 21][]

说明当HR bank用作非3V标准时需要添加约束：USE\_AS\_3V\_GPIO

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 22][]

![20200912173333487.png][]

约束信息的自动展开：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 23][]

其它：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 24][]

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[20200912175545361.png]: /images/20221123/1b6b956995184ea4a20f286439cc9866.png
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[https_www.intel.cn_content_www_cn_zh_programmable_documentation_prh1555609801770.html]: https://www.intel.cn/content/www/cn/zh/programmable/documentation/prh1555609801770.html
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