开源SoC整理

浅浅的花香味﹌ 2022-10-09 06:26 325阅读 0赞

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70][]

1、[https://docs.opentitan.org/][https_docs.opentitan.org]

2、rocket-riscv

3、optimsoc (openrisc)

4、西部数据开源riscv

[https://github.com/chipsalliance/Cores-SweRV][https_github.com_chipsalliance_Cores-SweRV]

**西数SweRV是一种32位顺序执行架构，双路超标量设计，9级流水线，支持SMT同步多线程**

**第一个版本Swe Core EH1采用台积电28nm工艺制造，运行频率高达1.8GHz，模拟性能可达4.9 CoreMark/MHz，略高于ARM A15。**

**SweRV Core EH2基本架构不变，工艺升级为台积电16nm FinFET造，以获得性能、功耗、面积的最佳平衡，模拟性能提升29％达到6.3 CoreMark/MHz，内核面积缩小39％仅为0.067平方毫米。**

[https://news.mydrivers.com/1/662/662375.htm][https_news.mydrivers.com_1_662_662375.htm]

5、openpiton

6、opensparct1

7、VexRiscv

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 1][]

[https://github.com/SpinalHDL/VexRiscv][https_github.com_SpinalHDL_VexRiscv]

8、Ibex RISC-V Core

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2][]

[https://github.com/lowRISC/ibex][https_github.com_lowRISC_ibex]

9，vivado risc-v (基于rocket-chip)

[https://github.com/eugene-tarassov/vivado-risc-v][https_github.com_eugene-tarassov_vivado-risc-v]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4][]

10、香山

中科院大学教授、中科院计算所研究员包云岗公布了国产开源高性能RISC-V处理器核心——香山。

[https://mp.weixin.qq.com/s/9JTeaZr-PAaVTXjGanso3w][https_mp.weixin.qq.com_s_9JTeaZr-PAaVTXjGanso3w]

11，openpiton

[https://github.com/PrincetonUniversity/openpiton][https_github.com_PrincetonUniversity_openpiton]

[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70]: /images/20221005/9702d30a00df41039bd273ef6ac64689.png
[https_docs.opentitan.org]: https://docs.opentitan.org/
[https_github.com_chipsalliance_Cores-SweRV]: https://github.com/chipsalliance/Cores-SweRV
[https_news.mydrivers.com_1_662_662375.htm]: https://news.mydrivers.com/1/662/662375.htm
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 1]: /images/20221005/181460784d13450983a6fe6cda0de473.png
[https_github.com_SpinalHDL_VexRiscv]: https://github.com/SpinalHDL/VexRiscv
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2]: /images/20221005/c3ecc9caef9d40989de137dab8592d19.png
[https_github.com_lowRISC_ibex]: https://github.com/lowRISC/ibex
[https_github.com_eugene-tarassov_vivado-risc-v]: https://github.com/eugene-tarassov/vivado-risc-v
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3]: /images/20221005/b053d0d29bcb455fb58b48246a76bfe3.png
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4]: /images/20221005/2ad26a81a23041db8c1339e400fd8523.png
[https_mp.weixin.qq.com_s_9JTeaZr-PAaVTXjGanso3w]: https://mp.weixin.qq.com/s/9JTeaZr-PAaVTXjGanso3w
[https_github.com_PrincetonUniversity_openpiton]: https://github.com/PrincetonUniversity/openpiton