Ubuntu内核优化问题

╰+攻爆jí腚メ 2022-09-18 05:56 156阅读 0赞

[http://forum.ubuntu.org.cn/about25110.html][http_forum.ubuntu.org.cn_about25110.html]

看来威盛的c3还是没有涉及阿

i386  
Original Intel’s i386 **CPU**.  
  
i486  
Intel’s i486 **CPU**. (No scheduling is implemented for this  
chip.)  
  
i586, pentium  
Intel Pentium **CPU** with no MMX support.  
  
pentium-mmx  
Intel PentiumMMX **CPU** based on Pentium core with MMX instruction  
set support.  
  
i686, pentiumpro  
Intel PentiumPro **CPU**.  
  
pentium2  
Intel Pentium2 **CPU** based on PentiumPro core with MMX instruc‐  
tion set support.  
  
pentium3, pentium3m  
Intel Pentium3 **CPU** based on PentiumPro core with MMX and SSE  
instruction set support.  
  
pentium-m  
Low power version of Intel Pentium3 **CPU** with MMX, SSE and SSE2  
instruction set support. Used by Centrino notebooks.  
  
pentium4, pentium4m  
Intel Pentium4 **CPU** with MMX, SSE and SSE2 instruction set sup‐  
port.  
  
prescott  
Improved version of Intel Pentium4 **CPU** with MMX, SSE, SSE2 and  
SSE3 instruction set support.  
  
nocona  
Improved version of Intel Pentium4 **CPU** with 64-bit extensions,  
MMX, SSE, SSE2 and SSE3 instruction set support.  
  
k6 AMD K6 **CPU** with MMX instruction set support.  
  
k6-2, k6-3  
Improved versions of AMD K6 **CPU** with MMX and 3dNOW! instruction  
set support.  
  
athlon, athlon-tbird  
AMD Athlon **CPU** with MMX, 3dNOW!, enhanced 3dNOW! and SSE  
prefetch instructions support.  
  
athlon-4, athlon-xp, athlon-mp  
Improved AMD Athlon **CPU** with MMX, 3dNOW!, enhanced 3dNOW! and  
full SSE instruction set support.  
  
k8, opteron, athlon64, athlon-fx  
AMD K8 core based CPUs with x86-64 instruction set support.  
(This supersets MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and  
64-bit instruction set extensions.)  
  
winchip-c6  
IDT Winchip C6 **CPU**, dealt in same way as i486 with additional  
MMX instruction set support.  
  
winchip2  
IDT Winchip2 **CPU**, dealt in same way as i486 with additional MMX  
and 3dNOW! instruction set support.  
  
**c3** Via **C3** **CPU** with MMX and 3dNOW! instruction set support. (No  
scheduling is implemented for this chip.)  
  
**c3**\-2  
Via **C3**\-2 **CPU** with MMX and SSE instruction set support. (No  
scheduling is implemented for this chip.)

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