ISE14.7工程移植到VIVADO

àì夳堔傛蜴生んèń 2022-09-04 11:58 595阅读 0赞

Vivado是Xilinx继ISE之后的FPGA开发环境，但是两者的工程存在较大差异，并不能直接转换。

这里主要参考Xilnx手册[UG911 (v2018.2) June 6, 2018][UG911 _v2018.2_ June 6_ 2018]做相关整理及记录。其中原工程中PL部分的源文件自然可以直接导入，主要问题难点在PS部分：

0、工程导入：这个功能只能导入一部分文件

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70][]

1、导入zynq soc

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 1][]

首先新建一个空白block design,添加zynq soc,如下图执行XPS导入:

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 2][]

有些参数还需要自己手动比对添加：

![2021081321160433.png][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 3][]

2、对于原ISE中的IP但在VIVADO中没有的，可以利用源码的方式添加：

原ISE中的库路径如下：主要都是VHDL源码（VHDL其实和Verilog类似，只是格式比较繁琐，主要分为:entity\[模块头部说明\]/architecture\[模块主体\]）

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 4][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 5][]

比如：AXI Slave Burst这个IP我在VIVADO ip catalog并没有找到：也许改了名字，这是我有疑问的地方

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 6][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 7][]

关于VHDL文件使用说明，如果不手动在文件属性栏指定编译的lib库的名字，则默认为work:

[UG901 (v2019.1) June 12, 2019 Synthesis][UG901 _v2019.1_ June 12_ 2019 Synthesis]  
![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 8][]

手动指定VHDL的编译库，实际操作发现只能一个一个文档修改：

[https://www.cnblogs.com/garylee/archive/2012/11/16/2773596.html][https_www.cnblogs.com_garylee_archive_2012_11_16_2773596.html]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 9][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 10][]

在第1步中zynq soc部分虽然已经同步过来但是其它子模块仍然需要自己手动添加：

ISE中的XPS的操作和VIVADO差距比较大：

ISE中的graphical view不同与vivado diagram,它只能用来查看当前连接的情况，并不能对ip模块进行操作，  
![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 11][]

实际操作需要切到其它页面：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 12][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 13][]

手动查看原IP参数，依次在vivado中添加进来。

一般来说有源文件的代码都可以在Diagram中右击Add Module，添加进来，但有一些却不可以：

根据UG994中描述：将鼠标悬停在不能添加的文件上面会有相关提示（不过有时候也没有）

![20210813211227503.png][]

导出AXI总线的问题：这个没有找到很好的解决办法，但是应该不影响实际功能：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 14][]

导出的AXI总线是没有时钟引出的，需要手动导出关联，如果只有一条可以通过如下方法解决：

[https://www.cnblogs.com/kingstacker/p/11595978.html][https_www.cnblogs.com_kingstacker_p_11595978.html]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 15][]

如果有多条则没有很好的办法来消除警告。

关于Diagram中模块内部使用不引出到引脚操作：比如

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 16][]

3、ucf转xdc

主要有两种方案一种利用综合的网表使用write\_xdc命令来生成位置约束:

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 17][]

另一种方法借助excel手动将UCF约束转为XDC约束

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 18][]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 19][]

导入效果如下：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 20][]

接下来需要一系列操作：

（1）删除空行

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 21][]

(2)刷选字段

![20210813210000513.png][]

如上两步基本可以较方便的把位置约束提取出来了。不得不说Excel确实是好东西！

每一种约束描述，具体可以参看UG911中描述：如KEEPER使用综合保留属性，防止综合时信号优化

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 22][]

最后需要移植的工程太复杂，一般还是用原来的环境:ISE14.7的安装要求如下：

[UG631 (v14.7) July 10, 2020][UG631 _v14.7_ July 10_ 2020]

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 23][]

参考连接：

1、[https://china.xilinx.com/support/documentation/sw\_manuals/xilinx2016\_1/ug911-vivado-migration.pdf][UG911 _v2018.2_ June 6_ 2018]

2、对于vivado block design操作可以参考文档：[UG994 (v2021.1) June 16, 2021Designing IP Subsystems Using IP Integrator][UG994 _v2021.1_ June 16_ 2021Designing IP Subsystems Using IP Integrator]

[UG911 _v2018.2_ June 6_ 2018]: https://china.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug911-vivado-migration.pdf
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[UG901 _v2019.1_ June 12_ 2019 Synthesis]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug901-vivado-synthesis.pdf
[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3UwMTEzMjk5Njc_size_16_color_FFFFFF_t_70 8]: /images/20220829/1fa344e450ed4ef78eee772549dafab7.png
[https_www.cnblogs.com_garylee_archive_2012_11_16_2773596.html]: https://www.cnblogs.com/garylee/archive/2012/11/16/2773596.html
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[20210813211227503.png]: /images/20220829/2db70f5371954d9c9ae6fbf7f1fbb895.png
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[https_www.cnblogs.com_kingstacker_p_11595978.html]: https://www.cnblogs.com/kingstacker/p/11595978.html
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[20210813210000513.png]: /images/20220829/f31623019b0e4b1190d1aeb7ac7f1cd0.png
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[UG631 _v14.7_ July 10_ 2020]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/irn.pdf
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[UG994 _v2021.1_ June 16_ 2021Designing IP Subsystems Using IP Integrator]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug994-vivado-ip-subsystems.pdf