FPGA数码管的显示总结

迈不过友情╰ 2022-09-03 00:13 210阅读 0赞

1：由于视觉暂留效应，首先生成1k 的时钟。

2： 数码管位选和 段选，确定信号是高电平有效，还是低电平有效。

3： 知道0~f 数字用数码管怎么表示。

4： 仿真的情况： 应该是生成1k 时钟的时候，再输入显示的数据。

源代码：

`timescale 1ns / 1ps
    //
    // Company: 
    // Engineer: 
    // 
    // Create Date: 2021/08/04 10:10:22
    // Design Name: 
    // Module Name: HEX_TOP
    // Project Name: 
    // Target Devices: 
    // Tool Versions: 
    // Description: 
    // 
    // Dependencies: 
    // 
    // Revision:
    // Revision 0.01 - File Created
    // Additional Comments:
    // 
    //
    
    
    module HEX_TOP(
          input clk,
    	  input reset_n,
    	  input [31:0]  disp_data,
    	  output reg [7:0] seg,
    	  output reg [7:0] sel 
    	
        );
    	
    	reg [15:0] clk_cnt;// 25000;
    	//reg [17:0]  cnt_disp;//12500;
        reg clk_1k;
        reg [2:0]  sel_cnt;
    	reg [3:0]  num;
    	always@(posedge clk or negedge reset_n)begin
             if(!reset_n)begin
         		clk_cnt <=  16'd0; 
                clk_1k <= 1'b0;			
    		 end 
    		 else if(clk_cnt == 12500-1)begin
                 clk_cnt <= 16'd0;	
                 clk_1k <= ~clk_1k;			 
    		 end 
    		 else 
    		      clk_cnt <= clk_cnt+1'b1;
    	end 
    	   
    	always@(posedge clk_1k or negedge reset_n)begin 
    	      if(!reset_n)
                  sel_cnt<=3'd0;    		   		  
    		  else 
    		      sel_cnt <= sel_cnt+1'b1;
        end 		  
    	
        always@(posedge clk_1k)begin 
             case(sel_cnt) 
    		     0:num <= disp_data[3:0];
    			 1:num <= disp_data[7:4];
    			 2:num <= disp_data[11:8];
    			 3:num <= disp_data[15:12];
    			 4:num <= disp_data[19:16];
    			 5:num <= disp_data[23:20];
    			 6:num <= disp_data[27:24];
    			 7:num <= disp_data[31:28];   
    		    
    		 endcase  
        end 	
    	
         always@(posedge clk_1k)begin 
             case(sel_cnt)
    		     0:sel <= 8'b0000_0001;
    			 1:sel <= 8'b0000_0010;
    			 2:sel <= 8'b0000_0100;
    			 3:sel <= 8'b0000_1000;
    			 4:sel <= 8'b0001_0000;
    			 5:sel <= 8'b0010_0000;
    			 6:sel <= 8'b0100_0000;
    			 7:sel <= 8'b1000_0000;
    		     default: sel <= 8'b0000_0000;
    		
    		 endcase  
        end 	
                            		 
    	always@(posedge clk_1k)begin 
    	   case(num)
    	         0:  seg <= 8'hc0;
    			 1:  seg <= 8'hf9;
    			 2:  seg <= 8'ha4;
    			 3:  seg <= 8'hb0;
    			 4:  seg <= 8'h99;
    			 5:  seg <= 8'h92;
    			 6:  seg <= 8'h82;
    			 7:  seg <= 8'hf8;
    			 8:  seg <= 8'h80;
    			 9:  seg <= 8'h90;
    			 10: seg <= 8'h88;
    			 11: seg <= 8'h83;
    			 12: seg <= 8'hc6;
    			 13: seg <= 8'ha1;
    			 14: seg <= 8'h86;
    			 15: seg <= 8'h8e;
    		     default:seg <= 8'hff;
    	    endcase 
    	end 
        	  
    		  
    endmodule

仿真代码：

`timescale 1ns / 1ps
    //
    // Company: 
    // Engineer: 
    // 
    // Create Date: 2021/08/04 14:18:44
    // Design Name: 
    // Module Name: hex_tb
    // Project Name: 
    // Target Devices: 
    // Tool Versions: 
    // Description: 
    // 
    // Dependencies: 
    // 
    // Revision:
    // Revision 0.01 - File Created
    // Additional Comments:
    // 
    //
    
    
    module hex_tb();
    	
    	 
    	  reg  clk;
    	  reg reset_n;
    	  reg [31:0] disp_data;
    	  wire  [7:0] seg;
    	  wire  [7:0] sel ;
    	
    	 HEX_TOP  HEX_TOP_inst1(
         .clk(clk),
    	 .reset_n(reset_n),
    	 .disp_data(disp_data),
    	 .seg(seg),
    	 .sel(sel)
        );
    	
    	initial begin
    	   reset_n   =0;
    	   clk=0;
    	   disp_data = 32'd0;
    	   #201;
    	   reset_n=1;
    	   #2010_0000;
    	   disp_data = 32'h12345678;
    	   #2000_0000;
    	   disp_data = 32'ha19bcd4;
    	   #200;
    	   $stop;
    	end 
    	always #20 clk =~ clk;
    	
    endmodule

仿真的波形显示：

![watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl80MjUyODA4OQ_size_16_color_FFFFFF_t_70][]

[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl80MjUyODA4OQ_size_16_color_FFFFFF_t_70]: /images/20220829/eb5b87eda346443bb6ae528e4520182c.png