stm32 FSMC-外扩SRAM IS62WV51216

曾经终败给现在 2022-06-09 03:39 162阅读 0赞

**引脚定义**  
![1][]![2][]

**FSMC配置步骤**

> 1.使能对应引脚GPIO时钟  
> 2.配置GPIO引脚模式  
> 3.使能FSMC时钟  
> 4.FSMC初始化  
> 5.存储器块使能

**举例**  
![1][1 1]

#define Bank1_SRAM3_ADDR ((u32)(0x68000000)) //首地址0x60000000，每块0x40000000
    
    void SRAM_gpio_init()
    {
        GPIO_InitTypeDef gpiof = 
        {
            GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
                GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15, //FSMC_A0 - FSMC_A9
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
        GPIO_InitTypeDef gpiog0_5 = 
        {
            GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5, //FSMC_A10 - FSMC_A15
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
        GPIO_InitTypeDef gpiod = 
        {
            GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | //FSMC_A15 - FSMC_A18
            GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_0 | GPIO_Pin_1 | //FSMC_D0 - FSMC_D3
                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10, //FSMC_D13 - FSMC_D15
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
        GPIO_InitTypeDef gpioe = 
        {
            //FSMC_D4 - FSMC_D12
            GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15, 
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
    
        GPIO_InitTypeDef gpioe0_1 = 
        {
            GPIO_Pin_0 | GPIO_Pin_1, //FSMC_NBL0-FSMC_NBL1
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
        GPIO_InitTypeDef gpiod4_5 = 
        {
            GPIO_Pin_4 | GPIO_Pin_5, //FSMC_NOE - FSMC_NWE
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
        GPIO_InitTypeDef gpiog10 = 
        {
            GPIO_Pin_10, //片选
            GPIO_Speed_50MHz,
            GPIO_Mode_AF_PP
        };
    
        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE);
    
        GPIO_Init(GPIOF, &gpiof);
        GPIO_Init(GPIOG, &gpiog0_5);
        GPIO_Init(GPIOD, &gpiod);
        GPIO_Init(GPIOE, &gpioe);
        GPIO_Init(GPIOE, &gpioe0_1);
        GPIO_Init(GPIOD, &gpiod4_5);
        GPIO_Init(GPIOG, &gpiog10);
    }
    
    void FSMC_sram_init()
    {
        FSMC_NORSRAMInitTypeDef fsmc = {
       0};
        FSMC_NORSRAMTimingInitTypeDef FSMC_ReadWriteTimingStruct = {
       0};
    
        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
    
        FSMC_ReadWriteTimingStruct.FSMC_AddressSetupTime = 0x00;
        FSMC_ReadWriteTimingStruct.FSMC_AddressHoldTime = 0x00;
        FSMC_ReadWriteTimingStruct.FSMC_DataSetupTime = 0x08;
        FSMC_ReadWriteTimingStruct.FSMC_BusTurnAroundDuration = 0x00;
        FSMC_ReadWriteTimingStruct.FSMC_CLKDivision = 0x00;
        FSMC_ReadWriteTimingStruct.FSMC_DataLatency = 0x00;
        FSMC_ReadWriteTimingStruct.FSMC_AccessMode = FSMC_AccessMode_A;
    
        fsmc.FSMC_Bank = FSMC_Bank1_NORSRAM3;
        fsmc.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
        fsmc.FSMC_MemoryType = FSMC_MemoryType_SRAM;
        fsmc.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
        fsmc.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
        fsmc.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
        fsmc.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
        fsmc.FSMC_WrapMode = FSMC_WrapMode_Disable;
        fsmc.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
        fsmc.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
        fsmc.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
        fsmc.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable; //扩展模式使能
        fsmc.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
        fsmc.FSMC_ReadWriteTimingStruct = &FSMC_ReadWriteTimingStruct;
        fsmc.FSMC_WriteTimingStruct = &FSMC_ReadWriteTimingStruct;
        FSMC_NORSRAMInit(&fsmc);
    
        FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
    }
    
    void SRAM_read(u8 *buf, u32 addr, u32 num)
    {
        u32 i = 0;
    
        for(i = 0; i < num; i++)
        {
            buf[i] = *(u8*)(Bank1_SRAM3_ADDR + addr + i);
        }
    }
    
    void SRAM_write(u8 *buf, u32 addr, u32 num)
    {
        u32 i = 0;
        u8 *p = (u8*)(Bank1_SRAM3_ADDR + addr);
    
        for(i = 0; i < num; i++)
        {
            *(p + i) = buf[i];
        }
    }

[1]: https://img-blog.csdn.net/20170826103802076?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvemhhbmd4dWVjaGFvXw==/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast
[2]: /images/20220609/2ab8cee8cc7b4144a8cf7f0168cc50d8.png
[1 1]: /images/20220609/acc3eeed35fd42ec83b85f468bcafc7e.png