Cortex-M0/M0+ System Control Space Registers

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### SysTick Register Summary ###

<table> 
 <thead> 
  <tr> 
   <th>Address</th> 
   <th>Name</th> 
   <th>CMSIS symbal</th> 
   <th>Full name</th> 
  </tr> 
 </thead> 
 <tbody> 
  <tr> 
   <td>0xE000E010</td> 
   <td>SYST_CSR</td> 
   <td>SysTick-&gt;CTRL</td> 
   <td>SysTick Control and Status Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E014</td> 
   <td>SYST_RVR</td> 
   <td>SysTick-&gt;LOAD</td> 
   <td>SysTick Reload Value Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E018</td> 
   <td>SYST_CVR</td> 
   <td>SysTick-&gt;VAL</td> 
   <td>SysTick Current Value Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E01C</td> 
   <td>SYST_CALIB</td> 
   <td>SysTick-&gt;CALIB</td> 
   <td>SysTick Calibration Register</td> 
  </tr> 
 </tbody> 
</table>

### NVIC Register Summary ###

<table> 
 <thead> 
  <tr> 
   <th>Address</th> 
   <th>Name</th> 
   <th>CMSIS symbal</th> 
   <th>Full name</th> 
  </tr> 
 </thead> 
 <tbody> 
  <tr> 
   <td>0xE000E100</td> 
   <td>ISER</td> 
   <td>NVIC-&gt;ISER</td> 
   <td>Interrupt Set Enable Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E104 ~ 0xE000E17C</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000E180</td> 
   <td>ICER</td> 
   <td>NVIC-&gt;ICER</td> 
   <td>Interrupt Clear Enable Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E184 ~ 0xE000E1FC</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000E200</td> 
   <td>ISPR</td> 
   <td>NVIC-&gt;ISPR</td> 
   <td>Interrupt Set Pending Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E204 ~ 0xE000E27C</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000E280</td> 
   <td>ICPR</td> 
   <td>NVIC-&gt;ICPR</td> 
   <td>Interrupt Clear Pending Register</td> 
  </tr> 
  <tr> 
   <td>0xE000E284 ~ 0xE000E2FC</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000E300 ~ 0xE000E3FC</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000E400</td> 
   <td>IPR0</td> 
   <td>NVIC-&gt;IPR[0]</td> 
   <td>Interrupt Priority Register 0</td> 
  </tr> 
  <tr> 
   <td>0xE000E404</td> 
   <td>IPR1</td> 
   <td>NVIC-&gt;IPR[1]</td> 
   <td>Interrupt Priority Register 1</td> 
  </tr> 
  <tr> 
   <td>0xE000E408</td> 
   <td>IPR2</td> 
   <td>NVIC-&gt;IPR[2]</td> 
   <td>Interrupt Priority Register 2</td> 
  </tr> 
  <tr> 
   <td>0xE000E40C</td> 
   <td>IPR3</td> 
   <td>NVIC-&gt;IPR[3]</td> 
   <td>Interrupt Priority Register 3</td> 
  </tr> 
  <tr> 
   <td>0xE000E410</td> 
   <td>IPR4</td> 
   <td>NVIC-&gt;IPR[4]</td> 
   <td>Interrupt Priority Register 4</td> 
  </tr> 
  <tr> 
   <td>0xE000E414</td> 
   <td>IPR5</td> 
   <td>NVIC-&gt;IPR[5]</td> 
   <td>Interrupt Priority Register 5</td> 
  </tr> 
  <tr> 
   <td>0xE000E418</td> 
   <td>IPR6</td> 
   <td>NVIC-&gt;IPR[6]</td> 
   <td>Interrupt Priority Register 6</td> 
  </tr> 
  <tr> 
   <td>0xE000E41C</td> 
   <td>IPR7</td> 
   <td>NVIC-&gt;IPR[7]</td> 
   <td>Interrupt Priority Register 7</td> 
  </tr> 
 </tbody> 
</table>

### SCB Register Summary ###

<table> 
 <thead> 
  <tr> 
   <th>Address</th> 
   <th>Name</th> 
   <th>CMSIS symbal</th> 
   <th>Full name</th> 
  </tr> 
 </thead> 
 <tbody> 
  <tr> 
   <td>0xE000ED00</td> 
   <td>CPUID</td> 
   <td>SCB-&gt;CPUID</td> 
   <td>CPU ID (Identity) Base register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED04</td> 
   <td>ICSR</td> 
   <td>SCB-&gt;ICSR</td> 
   <td>Interrupt Control State Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED08</td> 
   <td>VTOR</td> 
   <td>SCB-&gt;VTOR</td> 
   <td>Vector Table Offset Register(Cortex-M0+ only)</td> 
  </tr> 
  <tr> 
   <td>0xE000ED0C</td> 
   <td>AIRCR</td> 
   <td>SCB-&gt;AIRCR</td> 
   <td>Application Interrupt and Reset Control Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED10</td> 
   <td>SCR</td> 
   <td>SCB-&gt;SCR</td> 
   <td>System Control Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED14</td> 
   <td>CCR</td> 
   <td>SCB-&gt;CCR</td> 
   <td>Configuration and Control Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED18</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000ED1C</td> 
   <td>SHPR2</td> 
   <td>SCB-&gt;SHP[0]</td> 
   <td>System Handler Priority Register 2</td> 
  </tr> 
  <tr> 
   <td>0xE000ED20</td> 
   <td>SHPR3</td> 
   <td>SCB-&gt;SHP[1]</td> 
   <td>System Handler Priority Register 3</td> 
  </tr> 
  <tr> 
   <td>0xE000ED24</td> 
   <td>SHCSR</td> 
   <td>SCB-&gt;SHCSR</td> 
   <td>System Handler Control and State Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED28</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000ED2C</td> 
   <td></td> 
   <td></td> 
   <td></td> 
  </tr> 
  <tr> 
   <td>0xE000ED30</td> 
   <td>DFSR</td> 
   <td></td> 
   <td>Debug Fault Status Register</td> 
  </tr> 
 </tbody> 
</table>

### MPU Register Summary(Cortex-M0+ only) ###

<table> 
 <thead> 
  <tr> 
   <th>Address</th> 
   <th>Name</th> 
   <th>CMSIS symbal</th> 
   <th>Full name</th> 
  </tr> 
 </thead> 
 <tbody> 
  <tr> 
   <td>0xE000ED90</td> 
   <td>MPU_TYPE</td> 
   <td>MPU-&gt;TYPE</td> 
   <td>MPU Type Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED94</td> 
   <td>MPU_CTRL</td> 
   <td>MPU-&gt;CTRL</td> 
   <td>MPU Control Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED98</td> 
   <td>MPU_RNR</td> 
   <td>MPU-&gt;RNR</td> 
   <td>MPU Region Number Register</td> 
  </tr> 
  <tr> 
   <td>0xE000ED9C</td> 
   <td>MPU_RBAR</td> 
   <td>MPU-&gt;RBAR</td> 
   <td>MPU Region Base Address Register</td> 
  </tr> 
  <tr> 
   <td>0xE000EDA0</td> 
   <td>MPU_RASR</td> 
   <td>MPU-&gt;RASR</td> 
   <td>MPU Region Attribute and Size Register</td> 
  </tr> 
 </tbody> 
</table>

### Debug Register Summary ###

<table> 
 <thead> 
  <tr> 
   <th>Address</th> 
   <th>Name</th> 
   <th>CMSIS symbal</th> 
   <th>Full name</th> 
  </tr> 
 </thead> 
 <tbody> 
  <tr> 
   <td>0xE000EDF0</td> 
   <td>DHCSR</td> 
   <td></td> 
   <td>Debug Halting Control and Status Register</td> 
  </tr> 
  <tr> 
   <td>0xE000EDF4</td> 
   <td>DCRSR</td> 
   <td></td> 
   <td>Debug Core Register Selector Register</td> 
  </tr> 
  <tr> 
   <td>0xE000EDF8</td> 
   <td>DCRDR</td> 
   <td></td> 
   <td>Debug Core Register Data Register</td> 
  </tr> 
  <tr> 
   <td>0xE000EDFC</td> 
   <td>DEMCR</td> 
   <td></td> 
   <td>Debug Exception Monitor Control Register</td> 
  </tr> 
 </tbody> 
</table>

### IDs Register Summary ###

<table> 
 <thead> 
  <tr> 
   <th>Address</th> 
   <th>Name</th> 
   <th>CMSIS symbal</th> 
   <th>Full name</th> 
  </tr> 
 </thead> 
 <tbody> 
  <tr> 
   <td>0xE000EFD0 [7:0]</td> 
   <td>PID4</td> 
   <td></td> 
   <td>Peripheral ID4</td> 
  </tr> 
  <tr> 
   <td>0xE000EFD4 [7:0]</td> 
   <td>PID5</td> 
   <td></td> 
   <td>Peripheral ID5</td> 
  </tr> 
  <tr> 
   <td>0xE000EFD8 [7:0]</td> 
   <td>PID6</td> 
   <td></td> 
   <td>Peripheral ID6</td> 
  </tr> 
  <tr> 
   <td>0xE000EFDC [7:0]</td> 
   <td>PID7</td> 
   <td></td> 
   <td>Peripheral ID7</td> 
  </tr> 
  <tr> 
   <td>0xE000EFE0 [7:0]</td> 
   <td>PID0</td> 
   <td></td> 
   <td>Peripheral ID0</td> 
  </tr> 
  <tr> 
   <td>0xE000EFE4 [7:0]</td> 
   <td>PID1</td> 
   <td></td> 
   <td>Peripheral ID1</td> 
  </tr> 
  <tr> 
   <td>0xE000EFE8 [7:0]</td> 
   <td>PID2</td> 
   <td></td> 
   <td>Peripheral ID2</td> 
  </tr> 
  <tr> 
   <td>0xE000EFEC [7:0]</td> 
   <td>PID3</td> 
   <td></td> 
   <td>Peripheral ID3</td> 
  </tr> 
  <tr> 
   <td>0xE000EFF0 [7:0]</td> 
   <td>CID0</td> 
   <td></td> 
   <td>Component ID0</td> 
  </tr> 
  <tr> 
   <td>0xE000EFF4 [7:0]</td> 
   <td>CID1</td> 
   <td></td> 
   <td>Component ID1</td> 
  </tr> 
  <tr> 
   <td>0xE000EFF8 [7:0]</td> 
   <td>CID2</td> 
   <td></td> 
   <td>Component ID2</td> 
  </tr> 
  <tr> 
   <td>0xE000EFFC [7:0]</td> 
   <td>CID3</td> 
   <td></td> 
   <td>Component ID3</td> 
  </tr> 
 </tbody> 
</table>