ROM and RAM remapping(ARM)

朱雀 2022-05-25 07:35 228阅读 0赞

摘自: [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Beihhaag.html][http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0471c_Beihhaag.html]

文档: ARM Compiler toolchain  Developing Software for ARM Processors.pdf

就不翻译了, 水平有限, 费时间, 免得误人子弟. 见谅则个!  ^\_^

=================================================================================================================

### Note ###

This information does not apply to ARMv6-M and ARMv7-M profiles.

You must consider what sort of memory your system has at address `0x0`, the address of the first instruction executed.

### Note ###

This information assumes that an ARM processor begins fetching instructions at `0x0`. This is the standard behavior for systems based on ARM processors. However, some ARM processors can be configured to begin fetching instructions from `0xFFFF0000`.

There has to be a valid instruction at `0x0` at startup, so you must have nonvolatile memory located at `0x0` at the moment of power-on reset. One way to achieve this is to have ROM located at `0x0`. However, there are some drawbacks to this configuration.

### ![Show/hide][Show_hide]Example ROM/RAM remapping ###

The following example shows a solution implementing ROM/RAM remapping after reset. The constants shown in this example are specific to the Versatile board, but the same method is applicable to any platform that implements remapping in a similar way. Scatter-loading description files must describe the memory map after remapping.

**Example 5. ROM/RAM remapping**

;  System memory locations
    Versatile_ctl_reg     EQU 0x101E0000 ; Address of control register
    DEVCHIP_Remap_bit     EQU 0x100      ; Bit 8 is remap bit of control register
        ENTRY
    ; Code execution starts here on reset
    ; On reset, an alias of ROM is at 0x0, so jump to 'real' ROM.
            LDR     pc, =Instruct_2
    Instruct_2 
    ; Remap by setting remap bit of the control register
    ; Clear the DEVCHIP_Remap_bit by writing 1 to bit 8 of the control register
            LDR     R1, =Versatile_ctl_reg
            LDR     R0, [R1]
            ORR     R0, R0, #DEVCHIP_Remap_bit
            STR     R0, [R1]
    ; RAM is now at 0x0.
    ; The exception vectors must be copied from ROM to RAM
    ; The copying is done later by the C library code inside __main
    ; Reset_Handler follows on from here

[http_infocenter.arm.com_help_index.jsp_topic_com.arm.doc.dui0471c_Beihhaag.html]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Beihhaag.html
[Show_hide]: /images/20220525/50ee33cf7d4c487493be113d71869411.png