setup_arch()函数分析4--cpu_init

太过爱你忘了你带给我的痛 2022-03-26 15:24 184阅读 0赞

arch/arm/kernel/setup.c  
struct stack \{  
    u32 irq\[3\];  
    u32 abt\[3\];  
    u32 und\[3\];  
\} \_\_\_\_cacheline\_aligned;  
  
/\*  
 \* cpu\_init - initialise one CPU.  
 \*  
 \* cpu\_init sets up the per-CPU stacks.  
 \*/  
arm的R13是bank register，arm的七种处理器模式有各自的R13(user模式和system模式共用一个,总共六个不同的R13)，也就是arm汇编默认的 SP(堆栈指针),就是说一旦产生了模式切换(IRQ，FIQ，异常等), 接着的代码就使用模式对应的SP.cpu\_init就是对用到的IRQ, ABT, UND模式的SP都作了初始化  
void cpu\_init(void) //设置cpu堆栈  
\{  
    unsigned int cpu = smp\_processor\_id(); //获取cpu的id  
    struct stack \*stk = &stacks\[cpu\];  
  
    if (cpu >= NR\_CPUS) \{  //对于ARM NR\_CPUS为1  
        printk(KERN\_CRIT "CPU%u: bad primary CPU number\\n", cpu);  
        BUG();  
    \}  
  
    /\*  
     \* Define the placement constraint for the inline asm directive below.  
     \* In Thumb-2, msr with an immediate value is not allowed.  
     \*/  
\#ifdef CONFIG\_THUMB2\_KERNEL  
\#define PLC    "r"  
\#else  
\#define PLC    "I"  
\#endif  
  
    /\*  
     \* setup stacks for re-entrant exception handlers  
     \*/  
    \_\_asm\_\_ (  
    "msr    cpsr\_c, %1\\n\\t"   //切换到IRQ\_MODE  
    "add    r14, %0, %2\\n\\t"    
    "mov    sp, r14\\n\\t"     //设置r13\_irq，此时sp是r13\_irq  
    "msr    cpsr\_c, %3\\n\\t"  //切换到ABT\_MODE  
    "add    r14, %0, %4\\n\\t"  
    "mov    sp, r14\\n\\t"     //设置r13\_abt，此时sp是r13\_abt  
    "msr    cpsr\_c, %5\\n\\t"  //切换到UND\_MODE  
    "add    r14, %0, %6\\n\\t"  
    "mov    sp, r14\\n\\t"   //设置r13\_und，此时sp是r13\_und  
    "msr    cpsr\_c, %7"    //切换回SVC\_MODE  
        :  
        : "r" (stk),  
          PLC (PSR\_F\_BIT | PSR\_I\_BIT | IRQ\_MODE),  
          "I" (offsetof(struct stack, irq\[0\])),  
          PLC (PSR\_F\_BIT | PSR\_I\_BIT | ABT\_MODE),  
          "I" (offsetof(struct stack, abt\[0\])),  
          PLC (PSR\_F\_BIT | PSR\_I\_BIT | UND\_MODE),  
          "I" (offsetof(struct stack, und\[0\])),  
          PLC (PSR\_F\_BIT | PSR\_I\_BIT | SVC\_MODE)  
        : "r14");  
\}  
可以看到,IRQ, ABT, UND模式的堆栈大小都只有3个int,  
你可能会问,进入这三个模式后, 怎么保存大量的寄存器?  
呵呵,进入这三种模式后,linux会把模式切换到SVC\_MODE,使用的是SVC\_MODE的堆栈.我们看一下在arch/arm/kernel/entry-armv.S中的汇编代码  
1040 /\*  
1041  \* Vector stubs.  
1042  \*  
1043  \* This code is copied to 0xffff0200 so we can use branches in the  
1044  \* vectors, rather than ldr's.  Note that this code must not  
1045  \* exceed 0x300 bytes.  
1046  \*  
1047  \* Common stub entry macro:  
1048  \*   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC  
1049  \*  
1050  \* SP points to a minimal amount of processor-private memory, the address  
1051  \* of which is copied into r0 for the mode specific abort handler.  
1052  \*/  
1053         .macro  vector\_stub, name, mode, correction=0  
1054         .align  5  
1055  
1056 vector\_\\name:  
1057         .if \\correction  
1058         sub     lr, lr, \#\\correction  
1059         .endif  
1060  
1061         @  
1062         @ Save r0, lr\_<exception> (parent PC) and spsr\_<exception>  
1063         @ (parent CPSR)  
1064         @  
1065         stmia   sp, \{r0, lr\}            @ save r0, lr //R13\_<mode>保存两个int  
1066         mrs     lr, spsr  
1067         str     lr, \[sp, \#8\]            @ save spsr   //R13\_<mode>再保存一个int  
1068  
1069         @  
1070         @ Prepare for SVC32 mode.  IRQs remain disabled.  
1071         @  
1072         mrs     r0, cpsr  
1073         eor     r0, r0, \#(\\mode ^ SVC\_MODE | PSR\_ISETSTATE) //切换到SVC,之后的堆栈操作都用R13\_svc，sp都是R13\_svc的值  
1074         msr     spsr\_cxsf, r0  
1075  
1076         @  
1077         @ the branch table must immediately follow this code  
1078         @  
1079         and     lr, lr, \#0x0f  
1080  THUMB( adr     r0, 1f                  )  
1081  THUMB( ldr     lr, \[r0, lr, lsl \#2\]    )  
1082         mov     r0, sp  
1083  ARM(   ldr     lr, \[pc, lr, lsl \#2\]    )  
1084         movs    pc, lr                  @ branch to handler in SVC mode  
1085 ENDPROC(vector\_\\name)  
  
/\*  
 \* PSR bits  
 \*/  
\#define USR26\_MODE    0x00000000  
\#define FIQ26\_MODE    0x00000001  
\#define IRQ26\_MODE    0x00000002  
\#define SVC26\_MODE    0x00000003  
\#define USR\_MODE    0x00000010  
\#define FIQ\_MODE    0x00000011  
\#define IRQ\_MODE    0x00000012  
\#define SVC\_MODE    0x00000013  
\#define ABT\_MODE    0x00000017  
\#define UND\_MODE    0x0000001b  
\#define SYSTEM\_MODE    0x0000001f  
\#define MODE32\_BIT    0x00000010  
\#define MODE\_MASK    0x0000001f  
\#define PSR\_T\_BIT    0x00000020  
\#define PSR\_F\_BIT    0x00000040  
\#define PSR\_I\_BIT    0x00000080  
\#define PSR\_A\_BIT    0x00000100  
\#define PSR\_E\_BIT    0x00000200  
\#define PSR\_J\_BIT    0x01000000  
\#define PSR\_Q\_BIT    0x08000000  
\#define PSR\_V\_BIT    0x10000000  
\#define PSR\_C\_BIT    0x20000000  
\#define PSR\_Z\_BIT    0x40000000  
\#define PSR\_N\_BIT    0x80000000