Verilog交通灯控制模块

骑猪看日落 2021-11-12 00:36 281阅读 0赞

**简介：**  
用Verilog编写行为模块模拟交通灯的控制时序。【注】该代码不可综合成电路网表。  
**代码实现：**

/*----------------------------------------------
    Filename: trafic_lights.v
    Function: 模拟交通灯的控制时序;[本程序不可综合]
    Author: Zhang Kaizhou
    Date: 2019-8-6 22:20:08
    -----------------------------------------------*/
    `timescale 1ns/1ns
    `define clock_period 100
    module trafic_lights(red, amber, green);
    	//端口定义
    	output red, amber, green;
    	reg clock, red, amber, green;
    	parameter on = 1, off = 0, red_tics = 350, 
    			  amber_tics = 30, green_tics = 200;
    	
    	//初始化
    	initial
    	begin
    		clock = 0; red = off; amber = off; green = off;
    	end
    	
    	//控制时序
    	always
    	begin
    		red = on;
    		light(red, red_tics);
    		amber = on;
    		light(amber, amber_tics);
    		green = on;
    		light(green, green_tics);
    	end
    	
    	//灯亮持续时间的任务
    	task light;
    		//端口定义
    		output color;
    		input [31 : 0] tics;
    		
    		//控制时序
    		begin
    			repeat(tics) @(posedge clock);
    			color = off;
    		end
    	endtask
    	
    	//产生时钟信号
    	always	#`clock_period clock = ~clock;
    endmodule

/*----------------------------------------------
    Filename: trafic_lights_tb.v
    Function: 测试程序
    Author: Zhang Kaizhou
    Date: 2019-8-6 22:21:02
    -----------------------------------------------*/
    `timescale 1ns/1ns
    module trafic_lights_tb;
    	wire red, amber, green;
    	
    	trafic_lights m0(.red(red), .amber(amber), .green(green));
    endmodule

**仿真结果：**  
![在这里插入图片描述][watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]  
以上仿真波形与代码所写控制时序逻辑一致，说明交通灯时序控制模块功能正常。

[watermark_type_ZmFuZ3poZW5naGVpdGk_shadow_10_text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3dlaXhpbl8zODY3OTkyNA_size_16_color_FFFFFF_t_70]: /images/20211108/2735a70f12c44eb09b19889bf999b8e6.png